Clock generating circuit

专利名称：Clock generating circuit发明人：Akira Takahashi申请号：US10500717申请日：20020116公开号：US07088155B2公开日：20060808

专利附图：

摘要：In a clock generation circuit generating a clock that is synchronized with areference signal, it is an object to provide stable clocks by controlling phase jitter in agenerated clock upon change of the reference signal, eliminate a stable-state phasedifference between the reference signal and the generated clock so that control is

eliminated, and allow the clock generation circuit to be integrated. The clock generationcircuit is configured with multiple stages of PLL circuits such that PLL circuits are providedfor reference signals , respectively, and one of outputs from the PLL circuits is selectedto be fed to a PLL circuit provided in a next stage. The phase fluctuation of a signalinputted to the PLL circuit upon change of the reference signal is reduced to control thephase jitter of the generated clock , thus allowing high loop gain in both the PLL circuitand the PLL circuit . Then, phase difference between the reference signal and thegenerated clock is eliminated to eliminate control involved, so that the clock generationcircuit may be integrated.

申请人：Akira Takahashi

地址：Tokyo JP

国籍：JP

代理机构：Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

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