Mechanism for error detection and reporting on a s

专利名称：Mechanism for error detection and

reporting on a synchronous bus

发明人：Munier, Jean-Marc,Peyronnenc,

Michel,Poret, Michel

申请号：EP88480002.0申请日：19880122公开号：EP0325078B1公开日：19920909

摘要：The subject mechanism 38 is implemented in a passive device 30 inserted on asynchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto whichdata are transferred between the two devices under control of tag lines and clock signalson lines 20 and 22, which are companion of the transferred data. It allows errors to bedetected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the errorsignals to be reported in a pseudo synchronous way on error bus 50, thanks to errordetection and reporting logic circuit 48 and pseudo syncho timing circuit 52.

申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION

地址：OLD ORCHARD ROAD; ARMONK, N.Y. 10504

代理机构：Lattard, Nicole

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