74LVT16374 • 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE OutputsJanuary 1999Revised June 2005
74LVT16374 • 74LVTH16374
Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The LVT16374 and LVTH16374 contain sixteen non-invert-ing D-type flip-flops with 3-STATE outputs and is intendedfor bus oriented applications. The device is byte controlled.A buffered clock (CP) and Output Enable (OE) are com-mon to each byte and can be shorted together for full 16-bitoperation.
The LVTH16374 data inputs include bushold, eliminatingthe need for external pull-up resistors to hold unusedinputs.
These flip-flops are designed for low-voltage (3.3V) VCCapplications, but with the capability to provide a TTL inter-face to a 5V environment. The LVT16374 and LVTH16374are fabricated with an advanced BiCMOS technology toachieve high speed operation similar to 5V ABT whilemaintaining a low power dissipation.
Features
sInput and output interface capability to systems at 5V VCCsBushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16374),also available without bushold feature (74LVT16374)sLive insertion/extraction permitted
sPower Up/Power Down high impedance provides glitch-free bus loadingsOutputs source/sink 32 mA/64 mA
sFunctionally compatible with the 74 series 16374sLatch-up performance exceeds 500 mAsESD performance:
Human-body model ! 2000VMachine model ! 200VCharged-device model ! 1000V
sAlso packaged in plastic Fine-Pitch Ball Grid Array(FBGA)
Ordering Code:
Order Number74LVT16374G(Note 1)(Note 2)74LVT16374MEA(Note 2)
74LVT16374MTD(Note 2)74LVTH16374G(Note 1)(Note 2)74LVTH16374MEA(Note 2)
74LVTH16374MTD(Note 2)
Package NumberBGA54A(Preliminary)MS48AMTD48BGA54AMS48AMTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300\" Wide48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300\" Wide48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
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74LVT16374 • 74LVTH16374Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin NamesOEnCPnI0–I15O0–O15NC
Description
Output Enable Input (Active LOW)Clock Pulse Input Inputs
3-STATE OutputsNo Connect
FBGA Pin Assignments
1
ABCDEFGHJ
O0O2O4O6O8O10O12O14O15
2NCO1O3O5O7O9O11O13NC
3OE1NCVCCGNDGNDGNDVCCNCOE2
4CP1NCVCCGNDGNDGNDVCCNCCP2
5NCI1I3I5I7I9I11I13NC
6I0I2I4I6I8I10I12I14I15
Truth Tables
Inputs
Pin Assignment for FBGA
CP1
OE1LLLHInputs
CP2
OE2LLLH
I8–I15HLXXI0–I7HLXX
OutputsO0–O7HLOoZOutputsO8–O15
HLOoZ
LX
(Top Thru View)
LX
H HIGH Voltage LevelL LOW Voltage LevelX Immaterial
Z HIGH Impedance
Oo Previous Oo before HIGH to LOW of CP
Functional Description
The LVT16374 and LVTH16374 consist of sixteenedge-triggered flip-flops with individual D-type inputs and3-STATE true outputs. The device is byte controlled witheach byte functioning identically, but independent of theother. The control pins can be shorted together to obtainfull 16-bit operation. Each byte has a buffered clock andbuffered Output Enable common to all flip-flops within thatbyte. The description which follows applies to each byte.
Each flip-flop will store the state of their individual D-typeinputs that meet the setup and hold time requirements onthe LOW-to-HIGH Clock (CPn) transition. With the OutputEnable (OEn) LOW, the contents of the flip-flops are avail-able at the outputs. When OEn is HIGH, the outputs go tothe high impedance state. Operation of the OEn input doesnot affect the state of the flip-flops.
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74LVT16374 • 74LVTH16374Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
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74LVT16374 • 74LVTH16374Absolute Maximum Ratings(Note 3)
SymbolVCCVIVOIIKIOKIOICCIGNDTSTG
Parameter
Supply VoltageDC Input VoltageDC Output VoltageDC Input Diode CurrentDC Output Diode CurrentDC Output Current
DC Supply Current per Supply PinDC Ground Current per Ground PinStorage Temperature
Value
Conditions
UnitsVV
Output in 3-STATE
Output in High or Low State (Note 4)VI GNDVO GNDVO ! VCCVO ! VCC
Output at High StateOutput at Low State
VmAmAmAmAmA
0.5 to 4.60.5 to 7.00.5 to 7.00.5 to 7.0505064128
r64r12865 to 150
qC
Recommended Operating Conditions
SymbolVCCVIIOHIOLTA
Supply VoltageInput Voltage
High-Level Output CurrentLow-Level Output CurrentFree-Air Operating Temperature
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
Parameter
Min2.70
Max3.65.5
UnitsVVmAmA
3264
400
8510
qCns/V
't/'VNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditionsbeyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
SymbolVIKVIHVILVOH
Parameter
Input Clamp Diode VoltageInput HIGH VoltageInput LOW VoltageOutput HIGH Voltage
VCC(V)2.72.7–3.62.7–3.62.7–3.62.73.0
VOL
Output LOW Voltage
2.72.73.03.03.0
II(HOLD)(Note 5)II(OD)(Note 5)II
Bushold Input Over-DriveCurrent to Change StateInput Current
Control PinsData Pins
IOFFIPU/PDIOZLIOZHIOZHPower Off Leakage CurrentPower Up/Down 3-STATEOutput Current
3-STATE Output Leakage Current3-STATE Output Leakage Current3-STATE Output Leakage CurrentBushold Input Minimum Drive
3.03.03.63.63.600–1.5V3.63.63.67575500500
10r151r100r1005510PAPAPAPAPAPA
VCC 0.22.42.0
0.20.50.40.50.55
PAPAVV
2.0
0.8
T A 40qC to 85qCMin
Max1.2
UnitsVV
Conditions
II 18 mAVO d 0.1V orVO t VCC 0.1VIOH 100 PAIOH 8 mAIOH 32 mAIOL 100 PAIOL 24 mAIOL 16 mAIOL 32 mAIOL 64 mAVI 0.8VVI 2.0V(Note 6)(Note 7)VI 5.5VVI 0V or VCCVI 0VVI VCC
0V d VI or VO d 5.5VVO 0.5V to 3.0VVI GND or VCCVO 0.5VVO 3.0VVCC VO d 5.5V
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74LVT16374 • 74LVTH16374DC Electrical Characteristics (Continued)
SymbolICCHICCLICCZICCZ'ICC
Parameter
Power Supply CurrentPower Supply CurrentPower Supply CurrentPower Supply Current
Increase in Power Supply Current(Note 8)
Note 5: Applies to bushold versions only (74LVTH16374).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
VCC(V)3.63.63.63.63.6
T A 40qC to 85qCMin
Max0.1950.190.190.2
UnitsmAmAmAmAmA
Conditions
Outputs HIGHOutputs LOWOutputs DisabledVCC d VO d 5.5V,Outputs DisabledOne Input at VCC 0.6VOther Inputs at VCC or GND
Dynamic Switching Characteristics (Note 9)
SymbolVOLPVOLV
Parameter
Quiet Output Maximum Dynamic VOLQuiet Output Minimum Dynamic VOL
VCC(V)3.33.3
Min
TA 25qCTyp0.80.8
Max
UnitsVV
ConditionsCL 50 pF, RL 500:
(Note 10)(Note 10)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA 40qC to 85qC, CL 50 pF, RL 500:
SymbolfMAXtPHLtPLHtPZLtPZHtPLZtPHZtStHtWtOSHLtOSLH
Setup TimeHold TimePulse Width
Output to Output Skew (Note 11)Output Disable Time
Parameter
Maximum Clock FrequencyPropagation DelayCP to On
Output Enable Time
VCC 3.3V r 0.3VMin1601.91.61.31.01.52.01.80.83.0
1.01.04.34.54.44.54.65.0Max
Min1601.91.61.31.01.52.02.00.13.0
1.01.04.65.25.05.44.85.4
VCC 2.7V
Max
MHznsnsnsnsnsnsnsUnits
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. Thespecification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
SymbolCINCOUT
Parameter
Input CapacitanceOutput Capacitance
Conditions
VCC Open, VI 0V or VCCVCC 3.0V, VO 0V or VCC
Typical48
UnitspFpF
Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
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74LVT16374 • 74LVTH16374Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
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74LVT16374 • 74LVTH16374Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300\" Wide
Package Number MS48A
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74LVT16374 • 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.www.fairchildsemi.com
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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
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