74FST338310−Bit Low PowerBus Exchange
The ON Semiconductor 74FST3383 is a 10−bit low power busexchange. The device is CMOS TTL compatible when operatingbetween 4 and 5.5 Volts. The device exhibits extremely low RON andadds nearly zero propagation delay. The device adds no noise orground bounce to the system.Featureshttp://onsemi.com
MARKINGDIAGRAMS24241SOIC−24DW SUFFIXCASE 751E1FST3383AWLYWW••••••••RON t 4 W TypicalLess Than 0.25 ns−Max Delay Through SwitchNearly Zero Standby CurrentNo Circuit BounceControl Inputs are TTL/CMOS CompatiblePin−For−Pin Compatible With QS3383, FST3383, CBT3383All Popular Packages: SOIC−24, TSSOP−24, QSOP−24All Devices in Package TSSOP are Inherently Pb−Free*24OEC0A0B0D0C1A1B1D1C2A2GND24FST3383ALYW1123456789101112242322212019181716151413VCCD4B4A4C4D3B3A3C3D2B2BX1TSSOP−24DT SUFFIXCASE 948H241QSOP−24QS SUFFIXCASE 492BAL, WLY, YYW, WW====24FST3383AWLYYWW1Figure 1. 24−Lead PinoutTRUTH TABLEOEHLLBXXLHA0−A4HIGH−Z StateC0−C4D0−D4B0−B4HIGH−Z StateD0−D4C0−C4FunctionDisconnectConnectExchangeAssembly LocationWafer LotYearWork WeekPIN NAMESPinOEBXA0−A4, B0−B4C0−C4, D0−D4DescriptionBus Switch EnableBus ExchangeBuses A, BBuses C, DNOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t CareORDERING INFORMATION
See detailed ordering and shipping information in the packagedimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
74FST3383/D
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74FST3383
A0
C0
B0D0
A4C4B4D4BXOEFigure 2. Logic DiagramORDERING INFORMATIONDevice Order Number74FST3383DW74FST3383DWR274FST3383DT74FST3383DTR274FST3383QS74FST3383QSRPackageSOIC−24SOIC−24TSSOP−24*(Pb−Free)TSSOP−24*(Pb−Free)QSOP−24QSOP−24Shipping†48 Units / Rail2500 Units / Tape & Reel96 Units / Rail2500 Units / Tape & Reel96 Units / Rail2500 Units / Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.
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74FST3383
MAXIMUM RATINGS
SymbolVCCVIVOIIKIOKIOICCIGNDTSTGTLTJqJA
DC Supply VoltageDC Input VoltageDC Output VoltageDC Input Diode CurrentDC Output Diode CurrentDC Output Sink Current
DC Supply Current per Supply PinDC Ground Current per Ground PinStorage Temperature Range
Lead Temperature, 1 mm from Case for 10 SecondsJunction Temperature Under BiasThermal Resistance
SOICTSSOPQSOPVI t GNDVO t GND
Parameter
Value*0.5 to )7.0*0.5 to )7.0*0.5 to )7.0
*50*50128$100$100*65 to )150
260)150125170200Level 1Oxygen Index: 28 to 34Human Body Model (Note 1)Machine Model (Note 2)Charged Device Model (Note 3)Above VCC and Below GND at 85°C (Note 4)UL 94 V−0 @ 0.125 inu2000u200N/A$500
VUnitVVVmAmAmAmAmA°C°C°C°C/W
MSLFRVESD
Moisture SensitivityFlammability RatingESD Withstand Voltage
ILatchup
Latchup PerformancemA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.
1.Tested to EIA/JESD22−A114−A.2.Tested to EIA/JESD22−A115−A.3.Tested to JESD22−C101−A.4.Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONSSymbolVCCVIVOTADt/DV
Supply VoltageInput VoltageOutput Voltage
Operating Free−Air TemperatureInput Transition Rise or Fall RateSwitch I/O
Switch Control InputVCC = 5.0 V $ 0.5 V
ParameterOperating, Data Retention Only(Note 5)
(HIGH or LOW State)
Min4.000*400
Max5.55.55.5)85DC5
UnitVVV°Cns/V
5.Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.http://onsemi.com
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74FST3383
DC ELECTRICAL CHARACTERISTICS
SymbolVIKVIHVILIIIOZRON
Parameter
Clamp Diode ResistanceHigh−Level Input VoltageLow−Level Input VoltageInput Leakage CurrentOFF−STATE Leakage CurrentSwitch On Resistance (Note 6)
0 v VIN v 5.5 V0 v A, B v VCCVIN = 0 V, IIN = 64 mAVIN = 0 V, IIN = 30 mAVIN = 2.4 V, IIN = 15 mAVIN = 2.4 V, IIN = 15 mA
ICCDICC
Quiescent Supply CurrentIncrease In ICC per Input
VIN = VCC or GND, IOUT = 0
One input at 3.4 V, Other inputs at VCC or GNDIIN = *18mA
Conditions
VCC(V)4.54.0 to 5.54.0 to 5.55.55.54.54.54.54.05.55.5
44811
2.0
0.8$1.0$1.077152032.5
mAmA
TA = *405C to )855CMin
Typ*
Max*1.2
UnitVVVmAmAW
*Typical values are at VCC = 5.0 V and TA = 25°C.
6.Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lowerof the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA = *405C to )855CCL = 50 pF, RU = RD = 500 WVCC = 4.5−5.5 VSymboltPHL, tPLHtPZH, tPZLtPHZ, tPLZ
ParameterProp Delay Bus to Bus (Note 7)Prop Delay, BX to An, Bn, Cn or DnOutput Enable Time, BX to An, Bn, Cn or DnOutput Enable Time, IOE to An, Bn, Cn or DnOutput Disable Time, BX to An, Bn, Cn or DnOutput Disable Time, IOE to An, Bn, Cn or DnVI = 7 V for tPZLVI = OPEN for tPZHVI = 7 V for tPLZVI = OPEN for tPHZ
ConditionsVI = OPEN1.01.01.01.01.0MinMax0.255.85.85.85.35.3
VCC = 4.0 VMin
Max0.256.56.56.56.26.2
nsnsUnitns
7.This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of thetypical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).CAPACITANCE (Note 8)
SymbolCINCI/O
Parameter
Control Pin Input CapacitancePort Input/Output CapacitanceVCC = 5.0 VVCC, OE = 5.0 VConditions
Typ613
Max
UnitpFpF
8.TA = )25°C, f = 1 MHz, Capacitance is characterized but not tested.http://onsemi.com
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74FST3383
AC Loading and Waveforms
VIFROMOUTPUTUNDERTEST500 WCL*500 WNOTES:1.Input driven by 50 W source terminated in 50 W.2.CL includes load and stray capacitance.*CL = 50 pFFigure 3. AC Test Circuittf = 2.5 nS90 %SWITCHINPUT1.5 V10 %tPLH1.5 V90 %1.5 Vtf = 2.5 nS3.0 V10 %tPLHGNDVOHOUTPUT1.5 VVOLFigure 4. Propagation Delaystf = 2.5 nStf = 2.5 nSENABLEINPUT90 %1.5 V10 %tPZLOUTPUT1.5 VtPZH10 %90 %1.5 VGNDtPZL3.0 VVOL + 0.3 VVOLtPHZLVOH1.5 VOUTPUTVOH − 0.3 VFigure 5. Enable/Disable Delays
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74FST3383
PACKAGE DIMENSIONS
SOIC−24D SUFFIXCASE 751E−04
ISSUE E
−A−2413−B−12XP0.010 (0.25)MBM112NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 (0.005) TOTAL INEXCESS OF D DIMENSION AT MAXIMUMMATERIAL CONDITION.DIMABCDFGJKMPRMILLIMETERSMINMAX15.2515.547.407.602.352.650.350.490.410.901.27 BSC0.230.320.130.290 8 __10.0510.550.250.75INCHESMINMAX0.6010.6120.2920.2990.0930.1040.0140.0190.0160.0350.050 BSC0.0090.0130.0050.0110 8 __0.3950.4150.0100.02924XD0.010 (0.25)MJTASBSFRC−T−SEATINGPLANE22XX 45_GKMhttp://onsemi.com
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74FST3383
PACKAGE DIMENSIONS
TSSOP−24DT SUFFIXCASE 948H−01
ISSUE A
24X REFKNOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH,PROTRUSIONS OR GATE BURRS. MOLD FLASHOR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.7.DIMENSION A AND B ARE TO BE DETERMINED ATDATUM PLANE −W−.DIMABCDFGHJJ1KK1LMMILLIMETERSMINMAX7.707.904.304.50−−−1.200.050.150.500.750.65 BSC0.270.370.090.200.090.160.190.300.190.256.40 BSC0 8 __INCHESMINMAX0.3030.3110.1690.177−−−0.0470.0020.0060.0200.0300.026 BSC0.0110.0150.0040.0080.0040.0060.0070.0120.0070.0100.252 BSC0 8 __0.10 (0.004)0.15 (0.006)TUSMTUSVS2XL/22413LPIN 1IDENT.112B−U−0.15 (0.006)TUSA−V−C0.10 (0.004)−T−SEATINGPLANEDGHKK1N0.25 (0.010)M−W−J1NFDETAIL EDETAIL ESECTION N−NJhttp://onsemi.com
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74FST3383
PACKAGE DIMENSIONS
QSOP−24QS SUFFIXCASE 492B−01ISSUE O
−A−RU−B−RAD.0.013 X 0.005DP. MAXRAD.0.005−0.010TYPQH x 45_MOLD PINMARKLP0.25 (0.010)MGTNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.THE BOTTOM PACKAGE SHALL BE BIGGER THANTHE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDEONLY). BOTTOM PACKAGE DIMENSION SHALLFOLLOW THE DIMENSION STATED IN THISDRAWING.4.PLASTIC DIMENSIONS DOES NOT INCLUDE MOLDFLASH OR PROTRUSIONS. MOLD FLASH ORPROTRUSIONS SHALL NOT EXCEED 6 MILS PERSIDE.5.BOTTOM EJECTOR PIN WILL INCLUDE THECOUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.INCHESDIMMAXMINA0.3370.344B0.1500.157C0.0610.068D0.0080.012F0.0160.035G0.025 BSCH0.0080.018J0.00980.0075K0.0040.010L0.2300.244M0 8 __N0 7 __P0.0270.037Q0.035 DIAR0.0350.045U0.0350.045V0 8 __MILLIMETERSMAXMIN8.568.743.813.991.551.730.200.310.410.890.64 BSC0.200.460.2490.1910.100.255.846.200 8 __0 7 __0.690.940.89 DIA0.891.140.891.140 8 __DETAIL EVN8 PLK−T−SEATINGPLANEMJMC24 PLDTBSFDETAIL E0.25 (0.010)ASON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com874FST3383/D
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