IS41C16256IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAMWITH EDO PAGE MODE
FEATURES
Extended Data-Out (EDO) Page Mode access cycleTTL compatible inputs and outputs; tristate I/ORefresh Interval: 512 cycles /8 ms
Refresh Mode: RAS-Only, CAS-before-RAS (CBR),Hidden
•Single power supply:
5V ± 10% (IS41C16256) 3.3V ± 10% (IS41LV16256)
•Byte Write and Byte Read operation via two CAS•Industrial Temperature Range -40oC to 85oC••••
DESCRIPTION
The ICSI IS41C16256 and IS41LV16256 is a 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memo-ries. The IS41C16256 offer an accelerated cycle accesscalled EDO Page Mode. EDO Page Mode allows 512 randomaccesses within a single row with access cycle time as shortas 10 ns per 16-bit word. The Byte Write control, of upper andlower byte, makes the IS41C16256 ideal for use in16-, 32-bit wide data bus systems.
These features make the IS41C16256and IS41LV16256 ideallysuited for high-bandwidth graphics, digital signal processing,high-performance computing systems, and peripheralapplications.
The IS41C16256 is packaged in a 40-pin 400mil SOJ and400mil TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)Min. EDO Page Mode Cycle Time (tPC)Min. Read/Write Cycle Time (tRC)
-25(5V)2510121045
-353510181260
-505014252090
-6060153025110
Unitnsnsnsnsns
PIN CONFIGURATIONS
40-Pin TSOP-2
VCCI/O0I/O1I/O2I/O3VCCI/O4I/O5I/O6I/O7 NCNCWERASNCA0A1A2A3VCC1112131415161718192030292827262524232221NCLCASUCASOEA8A7A6A5A4GND1234567891040393837363534333231GNDI/O15I/O14I/O13I/O12GNDI/O11I/O10I/O9I/O840-Pin SOJ
VCCI/O0I/O1I/O2I/O3VCCI/O4I/O5I/O6I/O7NCNCWERASNCA0A1A2A3VCC12345678910111213141516171819204039383736353433323130292827262524232221GNDI/O15I/O14I/O13I/O12GNDI/O11I/O10I/O9I/O8NCLCASUCASOEA8A7A6A5A4GNDPIN DESCRIPTIONS
A0-A8I/O0-15WEOERASUCASLCASVccGNDNC
Address InputsData Inputs/OutputsWrite EnableOutput EnableRow Address Strobe
Upper Column Address StrobeLower Column Address StrobePowerGroundNo Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errorswhich may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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IS41C16256IS41LV16256
FUNCTIONAL BLOCK DIAGRAMOEWELCASUCASCAS CLOCKGENERATORWE CONTROLLOGICSOE CONTROLLOGICCASWEOERASRAS CLOCKGENERATORDATA I/O BUSCOLUMN DECODERSSENSE AMPLIFIERSREFRESH COUNTERDATA I/O BUFFERSROW DECODERRASI/O0-I/O15MEMORY ARRAY262,144 x 16A0-A8ADDRESSBUFFERS2Integrated Circuit Solution Inc.
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IS41C16256IS41LV16256
TRUTH TABLE
FunctionStandbyRead: WordRead: Lower ByteRead: Upper ByteWrite: Word (Early Write)Write: Lower Byte (Early Write)Write: Upper Byte (Early Write)Read-Write(1,2)EDO Page-Mode Read(2)RASHLLLLLLLCASUCASHHLLLHHLLHLH→LH→LL→HH→LH→LH→LH→LLLHLLLHLLH→LH→LL→HH→LH→LH→LH→LLLHLWEXHHHLLLH→LHHHLLH→LH→LHLXXOEXLLLXXXL→HLLLXXL→HL→HLXXXAddress tR/tCXROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLNA/COLNA/NAROW/COLNA/COLROW/COLNA/COLROW/COLROW/COLROW/NAXI/OHigh-ZDOUTLower Byte, DOUTUpper Byte, High-ZLower Byte, High-ZUpper Byte, DOUTDINLower Byte, DINUpper Byte, High-ZLower Byte, High-ZUpper Byte, DINDOUT, DINDOUTDOUTDOUTDINDINDOUT, DINDOUT, DINDOUTDOUTHigh-ZHigh-ZEDO Page-Mode Write(1)EDO Page-ModeRead-Write(1,2)Hidden Refresh(2)RAS-Only RefreshCBR Refresh(3)L1st Cycle:L2nd Cycle:LAny Cycle:L1st Cycle:L2nd Cycle:L1st Cycle:L2nd Cycle:LReadL→H→LWriteL→H→LLH→LNotes:
1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).3.At least one of the two CAS signals must be active (LCAS or UCAS).
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IS41C16256IS41LV16256
Functional Description
The IS41C16256 and IS41LV16256 is a CMOS DRAMoptimized for high-speed bandwidth, low power applica-tions. During READ or WRITE cycles, each bit is uniquelyaddressed through the 18 address bits. These are en-tered 9 bits (A0-A8) at a time. The row address is latchedby the Row Address Strobe (RAS). The column addressis latched by the Column Address Strobe (CAS). RAS isused to latch the first nine bits and CAS is used the latternine bits.
The IS41C16256 and IS41LV16256 has two CAS controls,LCAS and UCAS. The LCAS and UCAS inputs internallygenerates a CAS signal functioning in an identical man-ner to the single CAS input on the other 256K x 16DRAMs. The key difference is that each CAS controls itscorresponding I/O tristate logic (in conjunction with OEand WE and RAS). LCAS controls I/O0 through I/O7 andUCAS controls I/O8 through I/O15.
The IS41C16256 and IS41LV16256 CAS function isdetermined by the first CAS (LCAS or UCAS) transitioningLOW and the last transitioning back HIGH. The two CAScontrols give the IS41C16256 both BYTE READ andBYTE WRITE cycle capabilities.
Refresh Cycle
To retain data, 512 refresh cycles are required in each8 ms period. There are two ways to refresh the memory.1.By clocking each of the 512 row addresses (A0 throughA8) with RAS at least once every 8 ms. Any read, write,read-modify-write or RAS-only cycle refreshes theaddressed row.
2.Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS,while holding CAS LOW. In CAS-before-RAS refreshcycle, an internal 9-bit counter provides the row ad-dresses and the external address inputs are ignored.CAS-before-RAS is a refresh-only mode and no dataaccess or device selection is allowed. Thus, the outputremains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns withina selected row to be randomly accessed at a high datarate.
In EDO page mode read cycle, the data-out is held to thenext CAS cycle’s falling edge, instead of the rising edge.For this reason, the valid data output time in EDO pagemode is extended compared with the fast page mode. Inthe fast page mode, the valid data output time becomesshorter as the CAS cycle time becomes shorter. Therefore,in EDO page mode, the timing margin in read cycle islarger than that of the fast page mode even if the CAS cycletime becomes shorter.
In EDO page mode, due to the extended data function, theCAS cycle time can be shorter than in the fast page modeif the timing margin is the same.
The EDO page mode allows both read and write opera-tions during one RAS cycle, but the performance isequivalent to that of the fast page mode in that case.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it isterminated by returning both RAS and CAS HIGH. Toensures proper device operation and data integrity anymemory cycle, once initiated, must not be ended oraborted before the minimum tRAS time has expired. A newcycle must not be initiated until the minimum prechargetime tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,whichever occurs last, while holding WE HIGH. Thecolumn address must be held for a minimum time specifiedby tAR. Data Out becomes valid only when tRAC, tAA, tCACand tOEA are all satisfied. As a result, the access time isdependent on the timing relationships between theseparameters.
Power-On
After application of the VCC supply, an initial pause of200 µs is required followed by a minimum of eight initial-ization cycles (any combination of cycles containing aRAS signal).
During power-on, it is recommended that RAS track withVCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS andWE, whichever occurs last. The input data must be validat or before the falling edge of CAS or WE, whicheveroccurs first.
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IS41C16256IS41LV16256
ABSOLUTE MAXIMUM RATINGS(1)
SymbolVTVCCIOUTPDTATSTG
Parameters
Voltage on Any Pin Relative to GNDSupply Voltage
Output CurrentPower Dissipation
Commercial Operation TemperatureIndustrial Operationg TemperatureStorage Temperature
5V3.3V5V3.3V
Rating–1.0 to +7.0–0.5 to +4.6–1.0 to +7.0–0.5 to +4.6
5010 to +70–40 to +85–55 to +125
UnitVVmAW°C°C°C
Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
SymbolVCCVIHVILTA
ParameterSupply VoltageInput High VoltageInput Low Voltage
Commercial Ambient TemperatureIndustrial Ambient Temperature
5V3.3V5V3.3V5V3.3V
Min.4.53.02.42.0–1.0–0.30–40
Typ.5.03.3——————
Max.5.53.6VCC + 1.0VCC + 0.30.80.87085
UnitVVV°C°C
CAPACITANCE(1,2)
SymbolCIN1CIN2CIO
Parameter
Input Capacitance: A0-A8
Input Capacitance: RAS, UCAS, LCAS, WE, OEData Input/Output Capacitance: I/O0-I/O15
Max.577
UnitpFpFpF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.2. Test conditions: TA = 25°C, f = 1 MHz.
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IS41C16256IS41LV16256
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)SymbolIILIIOVOHVOLICC1
Parameter
Input Leakage CurrentOutput Leakage CurrentOutput High Voltage LevelOutput Low Voltage LevelStandby Current: TTL
Test Condition
Any input 0V < VIN < Vcc
Other inputs not under test = 0VOutput is disabled (Hi-Z)0V < VOUT < VccIOH = –2.5 mAIOL =+2.1mA
RAS, LCAS, UCAS > VIHCommerical5V
Industrial5VCommerical3.3VIndustrial3.3VRAS, LCAS, UCAS > VCC – 0.2V
5V
3.3V-25-35-50-60-25-35-50-60-25-35-50-60-25-35-50-60Speed
Min.–10–102.4———————————————————————
Max.1010—0.4231210.5260230180170250220170160260230180170260230180170
UnitµAµAVVmA
ICC2ICC3
Standby Current: CMOSmAmA
Operating Current:RAS, LCAS, UCAS,
(2,3,4)
Random Read/WriteAddress Cycling, tRC = tRC (min.)Average Power Supply Current
Operating Current:RAS = VIL, LCAS, UCAS,
(2,3,4)
EDO Page ModeCycling tPC = tPC (min.)Average Power Supply Current
Refresh Current:RAS Cycling, LCAS, UCAS > VIH
(2,3)
RAS-OnlytRC = tRC (min.)Average Power Supply Current
Refresh Current:RAS, LCAS, UCAS CyclingCBR(2,3,5)tRC = tRC (min.)Average Power Supply Current
ICC4mA
ICC5mA
ICC6mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.4. Column-address is changed once each EDO page cycle.5. Enables on-chip refresh and address counters.
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IS41C16256IS41LV16256
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)SymboltRCtRACtCACtAAtRAStRPtCAStCPtCSHtRCDtASRtRAHtASCtCAHtARtRADtRALtRPCtRSHtCLZtCRPtODtOEtOEHCtOEPtOEStRCStRRHtRCHtWCHtWCRtWPtWPZtRWLtCWLtWCStDHR
Parameter
Random READ or WRITE Cycle TimeAccess Time from RAS(6, 7)Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)RAS Pulse WidthRAS Precharge TimeCAS Pulse Width(26)
CAS Precharge Time(9, 25)CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)Row-Address Setup TimeRow-Address Hold Time
Column-Address Setup Time(20)Column-Address Hold Time(20)Column-Address Hold Time(referenced to RAS)
RAS to Column-Address Delay Time(11)Column-Address to RAS Lead TimeRAS to CAS Precharge TimeRAS Hold Time(27)
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)Output Disable Time(19, 28, 29)Output Enable Time(15, 16)
OE HIGH Hold Time from CAS HIGHOE HIGH Pulse Width
OE LOW to CAS HIGH Setup TimeRead Command Setup Time(17, 20)Read Command Hold Time(referenced to RAS)(12)
Read Command Hold Time(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)Write Command Hold Time(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable OutputsWrite Command to RAS Lead Time(17)Write Command to CAS Lead Time(17, 21)Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
-25Min.Max.45———25154425100605198120735201010500051951075019
—25101210K—10K——17—————20—————128——————————————
-35Min.Max.60———352065351106063010180835301010500053051088030
—35101810K—10K——28—————20—————1210——————————————
-50Min.Max.90———503088501908084014250143530101050008408101414040
—50142510K—10K——36—————25—————1215——————————————
-60
Min.Max.Units110———604010106020010010401530015353—10105000105010101515040
—60153010K—10K——45—————30—————1215——————————————
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
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IS41C16256IS41LV16256
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)SymboltACHtOEHtDStDHtRWCtRWDtCWDtAWDtPCtRASPtCPAtPRWCtCOHtOFFtWHZtCLCHtCSRtCHRtORDtREFtT
Parameter
Column-Address Setup Time to CASPrecharge during WRITE CycleOE Hold Time from WE duringREAD-MODIFY-WRITE cycle(18)Data-In Setup Time(15, 22)Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle TimeRAS to WE Delay Time duringREAD-MODIFY-WRITE Cycle(14)CAS to WE Delay Time(14, 20)
(14) Column-Address to WE Delay Time
EDO Page Mode READ or WRITECycle Time(24)
RAS Pulse Width in EDO Page ModeAccess Time from CAS Precharge(15)EDO Page Mode READ-WRITECycle Time(24)
Data Output Hold after CASLOWOutput Buffer Turn-Off Delay fromCAS or RAS(13,15,19, 29)
Output Disable Delay from WELast CAS going LOW to First CASreturning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)CAS Hold Time (CBR REFRESH)(30, 21)OE Setup Time prior to RAS duringHIDDEN REFRESH CycleRefresh Period (512 Cycles)Transition Time (Rise or Fall)(2, 3)
-25Min.Max.15505653517211025—3253310570—1
—————————100K14——1515————850
-35Min.Max.15806804525301235—4053310880—1
—————————100K21——1515————850
-50Min.Max.1510081257034422050—475331010100—1
—————————100K27——1515————850
-60
Min.Max.Units15150101408036492550—565331010100—1
—————————100K34——1515————850
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
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IS41C16256IS41LV16256
Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2.VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3.In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4.If CAS and RAS = VIH, data output is High-Z.
5.If CAS = VIL, data output may contain data from the last valid READ cycle.6.Measured with a load equivalent to one TTL gate and 50 pF.
7.Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.8.Assumes that tRCD ≥ tRCD (MAX).
9.If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10.Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11.Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.12.Either tRCH or tRRH must be satisfied for a READ cycle.
13.tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14.tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read fromthe selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go backto VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.15.Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.17.Write command is defined as WE going low.
18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOWand OE is taken back to LOW after tOEH is met.
19.The I/Os are in open during READ cycles once tOD or tOFF occur.20.The first χCAS edge to transition LOW.21.The last χCAS edge to transition HIGH.
22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.
23.Last falling χCAS edge to first rising χCAS edge.
24.Last rising χCAS edge to next cycle’s last rising χCAS edge.25.Last rising χCAS edge to first falling χCAS edge.26.Each χCAS must meet minimum pulse width.27.Last χCAS to go LOW.
28.I/Os controlled, regardless UCAS and LCAS.
29.The 3 ns minimum is a parameter guaranteed by design.30.Enables on-chip refresh and address counters.
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IS41C16256IS41LV16256
READ CYCLE
tRCtRAStRPRAStCSHtCRPtRCDtRSHtCAStCLCHtRRHUCAS-LCAStARtRADtASRtRAHtASCtRALtCAHADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLCtOFF(1)RowI/OOEOpentOEValid DatatODOpentOESUndefinedDon’t CareNote:
1.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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IS41C16256IS41LV16256
EARLY WRITE CYCLE (OE = DON'T CARE)
tRCtRAStRPRAStCSHtCRPtRCDtRSHtCAStCLCHUCAS/LCAStARtRADtASRtRAHtASCtRALtCAHtACHADDRESSRowColumntCWLtRWLtWCRtWCStWCHtWPRowWEtDHRtDStDHI/OValid DataDon’t CareIntegrated Circuit Solution Inc.
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IS41C16256IS41LV16256
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWCtRAStRPRAStCSHtCRPtRCDtRSHtCAStCLCHUCAS-LCAStARtRADtASRtRAHtASCtCAHtACHtRALADDRESSRowtRCSColumntRWDtCWDtAWDRowtCWLtRWLtWPWEtAAtRACtCACtCLZtDStDHI/OOpentOEValid DOUTtODValid DINOpentOEHOEUndefinedDon’t Care12Integrated Circuit Solution Inc.
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IS41C16256IS41LV16256
EDO-PAGE-MODE READ CYCLE
tRASPtRPRAStCSHtCRPtRCDtCAS, tCLCHtPC(1)tCAS, tCPtCLCHtRSHtCPtCAS, tCLCHtCPUCAS/LCAStARtRADtASRtASCtCAHtASCtCAHtASCtRALtCAHADDRESSRowtRAHtRCSColumnColumnColumntRCHRowtRRHWEtAAtRACtCACtCLZtCACtCOHtAAtCPAtCACtCLZtAAtCPAtOFFI/OOpentOEtOESValid DataValid DatatOEHCtODtOESValid DatatOEOpentODOEtOEPUndefinedDon’t CareNote:
1.tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the tPC specifications.
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IS41C16256IS41LV16256
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASPtRPRAStCSHtCRPtRCDtCAS, tCLCHtCPtPCtCAS, tCLCHtCPtRSHtCAS, tCLCHtACHtRALtCAHtCPUCAS/LCAStARtRADtASRtASCtACHtCAHtASCtACHtCAHtASCADDRESSRowtRAHColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPRowWEtWCRtDHRtDStDHtDStDHtDStDHtRWLI/OOEValid DataValid DataValid DataDon’t Care14Integrated Circuit Solution Inc.
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IS41C16256IS41LV16256
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASPtRPRAStCSHtCRPtRCDtCAS, tCLCHtCPtPC / tPRWC(1)tCAS, tCLCHtCPtRSHtCAS, tCLCHtCPUCAS/LCAS tARtASRtRAHtRADtASCtCAHtASCtCAHtASCtRALtCAHADDRESSRowtRWDtRCSColumntCWLtWPtAWDtCWDColumntCWLtWPtAWDtCWDColumntRWLtCWLtWPtAWDtCWDRowWEtRACtCACtCLZ tAAtDStDHtAAtCPAtCACtCLZ tDStDHtAAtCPAtCACtCLZ tDHtDSI/OOpentOE DOUTDINtOD tOE DOUTDINtOD tOE DOUTDINtOD tOEH OpenOEUndefinedDon’t CareNote:
1.tPC in this diagram is for LATE write cycles only, tPC can be measured from falling edge of CAS to falling edge of CAS, or fromrising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
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IS41C16256IS41LV16256
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASPtRPRAStCSHtPCtCRPtRCDtCAStCPtCAS tPC tCPtRSHtCAStCPUCAS/LCAS tARtASRtRAHtRADtASCtCAHtASCtCAHtASCtACHtRALtCAHADDRESSRowtRCSColumn (A)Column (B)tRCHtWCSColumn (N) tWCHRowWEtRACtCACtAAtCPAtCACtCOH tAAtWHZtDStDHI/OOpentOE Valid Data (A)Valid Data (B)DINOpenOEDon’t Care16Integrated Circuit Solution Inc.
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IS41C16256IS41LV16256
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAStCSHtCRPtRCDtCAStCPUCAS/LCAStARtRADtASRtRAHtASCtCAHtASCADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLZtWPZColumntRCStWHZtCLZI/OOEOpentOEValid DataOpentODUndefinedDon’t CareRAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRCtRAStRPRAStCRPtRPCUCAS/LCAStASRtRAHADDRESSI/ORowOpenRowDon’t CareIntegrated Circuit Solution Inc.
DR001-0E 01/25/2002
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IS41C16256IS41LV16256
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRPtRAStRPtRASRAStRPCtCPtCHRtCSRtRPCtCSRtCHRUCAS/LCASI/OOpenHIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAStRPtRASRAStCRPtRCDtRSHtCHRUCAS/LCAStARtASRtRADtRAHtASCtRALtCAHADDRESSRowColumntAAtRACtCACtCLZtOFF(2)I/OOpentOEtORDValid DataOpentODOEUndefinedDon’t CareNotes:
1.A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.2.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
元器件交易网www.cecb2b.com
IS41C16256IS41LV16256
ORDERING INFORMATIONIS41C16256
Commercial Range: 0°C to 70°C
Speed (ns)Order Part No.
25355060
IS41C16256-25KIS41C16256-25TIS41C16256-35KIS41C16256-35TIS41C16256-50KIS41C16256-50TIS41C16256-60KIS41C16256-60T
Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2
ORDERING INFORMATION:IS41LV16256
Commercial Range: 0°C to 70°C
Speed (ns)Order Part No.
355060
IS41LV16256-35KIS41LV16256-35TIS41LV16256-50KIS41LV16256-50TIS41LV16256-60KIS41LV16256-60T
Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2
Industrial Range: -40°C to 85°C
Speed (ns)Order Part No.
25355060
IS41C16256-25KIIS41C16256-25TIIS41C16256-35KIIS41C16256-35TIIS41C16256-50KIIS41C16256-50TIIS41C16256-60KIIS41C16256-60TI
Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2
Industrial Range: -40°C to 85°C
Speed (ns)Order Part No.
355060
IS41LV16256-35KIS41LV16256-35TIS41LV16256-50KIIS41LV16256-50TIIS41LV16256-60KIIS41LV16256-60TI
Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
19
元器件交易网www.cecb2b.com
IS41C16256IS41LV16256
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140FAX: 886-2-26962252http://www.icsi.com.tw
20
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
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