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EDA基于FPGA的16×16点阵汉字显示

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江西理工大学应用科学学院EDA课程设计

江西理工大学应用科学学院

SOPC/EDA综合课程设计报告

设计题目：基于FPGA的16*16点阵汉字显示设计设计者：学号：班级：指导老师：王忠锋完成时间： 2012年1月6日

设计报告综合测试总评格式（10）

内容 (40) 图表（10）答辩（20）平时（20） 1

江西理工大学应用科学学院EDA课程设计

前言 ....................................................................................................... 3 第一章基本概要 ...................................................................................... 4 1.1 EDA的基本特征和设计流程 .................................................... 4 1.2 LED点阵显示特点 ........................................................................ 4 1.3 FPGA基本特点和设计的特点 ..................................................... 5 第二章系统设计 ...................................................................................... 7 2.1设计任务与要求 ............................................................................ 7 2.1.1设计要求 ................................................................................. 7 2.1.2 要求分析 ................................................................................ 8 2.2.设计方案 ........................................................................................ 8 2.3.LED的显示原理 ............................................................................ 9 2.4系统设计原理 ................................................................................ 9 第三章系统子程序设计 ........................................................................ 10 3.1 32进制计数器设计 ..................................................................... 10 3.2 16进制计数器设计 ..................................................................... 12 3.3 列驱动设计 ................................................................................. 14 3.4 行驱动设计 ................................................................................. 16 第四章原理图仿真波形 ........................................................................ 37 第五章课程设计体会 ............................................................................ 39 参考文献 ................................................................................................... 40

江西理工大学应用科学学院EDA课程设计

前言

现代文明的一个明显特征是城市中随处可见的五颜六色的广告宣传，其中大多都是由LED点阵制作的汉字或图形广告，广泛应用在银行、医院、酒店、火车站、运动场馆等各种公共场所。

汉字转动显示器的传统设计方法是用单片机来控制的，固然单片机方案具有价格低廉，程序编程灵活等特点，但由于单片机硬件资源术具有系统设计效率高、集成度好、保密性强、易的，未来对设计的变更和升级，总是要付出较多研发经费和较长投放市场周期的代价，甚至有可能需要重新设计。况且，在以显示为主的系统中，单片机的运算和控制等主要功能的利用率很低，单片机的上风得不到发挥，相当于很大的资源浪费。

采用EDA技术的自顶向下的模块化设计方法，借助相关开发软件，例如QualtusⅡ软件，将硬件描述语言——VHDL程序固化于具有丰富I／O口、内部逻辑和连线资源的FPGA(现场可编程门阵列)中。该技于修改、易于实现等优点，成为当今数字

江西理工大学应用科学学院EDA课程设计

第一章基本概要

1.1 EDA的基本特征和设计流程

EDA

技术是采用高级语言描述，具有系统级仿真和综合能力，它

主要采用并行工程(Concurrent Engineering)设计和自顶向下(Top-down)设计方法，其基本思想是从系统总体要求出发，分为行为描述、寄存器传输级描述、逻辑综合三个层次，将设计内容逐步细化，最后完成整体设计，这是一种全新的设计思想与设计理念。 EDA技术是将传统的“电路设计——硬件搭试——调试焊接”模式变为“功能设计——软件模拟——编程下载”方式，设计人员只需一台微机和相应的开发工具即可研制出各种功能电路。EDA技术将电子产品设计从软件编译、逻辑化简、逻辑综合、仿真优化、布局布线、逻辑适配、逻辑影射、编程下载、生成目标系统的全过程在计算机及其开发平台上自动处理完成。

1.2 LED点阵显示特点

1. 可以显示各种数字、文字、图表、曲线、图形；

2. 采用纯红、高绿作双基色发光器件，发光亮度高，色彩鲜艳、丰富；

3. 显示效果清晰、稳定、功耗低、寿命长；

4. 优质铝合金结构，磨沙、银镜或钛金不锈钢包边。尺寸和规格可根据需要灵活组合；

江西理工大学应用科学学院EDA课程设计

5. 支持各种计算机网络，编辑软件丰富、易用；

6. 适用于室内、外所有信息发布及广告宣传场所。如：银行、证券交易所、商场、市场、宾馆、洒楼、电信、邮政、医院、车站、机场等。

1.3 FPGA基本特点和设计的特点

基本特点：

1）采用FPGA设计ASIC电路(专用集成电路)，用户不需要投

片生产，就能得到合用的芯片。

2）FPGA可做其它全定制或半定制ASIC电路的中试样片。 3）FPGA内部有丰富的触发器和I/O引脚。

4）FPGA是ASIC电路中设计周期最短、开发费用最低、风险最小的器件之一。

5) FPGA采用高速CMOS工艺，功耗低，可以与CMOS、TTL电平兼容。

江西理工大学应用科学学院EDA课程设计

图1-1FPGA芯片的内部结构

FPGA 的主要特点是: 寄存器数目多, 采用查找表计数,适合时序逻辑设计。但是互连复杂, 由于互连采用开关矩阵,因而使得延时估计往往不十分准确。FPGA 也有其自身的局限性, 其一就是器件规模的,其二就是单元延迟比较大。所以, 在设计者选定某一FPGA器件后, 要求设计者对器件的结构、性能作深入的了解, 在体系结构设计时, 就必须考虑到器件本身的结构及性能, 尽可能使设计的结构满足器件本身的要求. 这样就增加了设计的难度。离开对FPGA 结构的详细了解, 设计人员就不可能优化设计。因而设计人员必须了解FPGA 器件的特性和, 熟悉FPGA 的结构。在了解FPGA 结构特点的基础上, 就可以利用VHDL 语言描写出高效的电路描述实现性能优化的电路。

江西理工大学应用科学学院EDA课程设计

第二章系统设计

2.1设计任务与要求

使用FPGA设计一个16×16的点阵显示的控制器，使点阵显

示器以两种花样显示“江西理工大学应用科学学院欢迎您！”

2.1.1设计要求

1·输出预定义“江、西、理、工、大、学、应、用、科、学、学、院、欢、迎、您、”十五个汉字； 2·输出汉字循环显示；

江西理工大学应用科学学院EDA课程设计

3·操作方便、可维护性高； 4·程序简捷、便于修改。 2.1.2 要求分析

根据设计要求可以分析出：点阵显示的花样有静态显示一个汉字，一屏一屏的显示汉字还有滚动显示汉字，还可以用亮着的灯显示汉字或者用暗着的灯显示汉字。

2.2.设计方案

方案一：用亮着的灯组合所要显示的字。

方案二：用暗着的灯组成所需要的字。两种花样显示都是用一屏一屏的显示方法。

图2-1 方案一示例图2-2 方案二示例

江西理工大学应用科学学院EDA课程设计

2.3.LED的显示原理

16×16扫描LED点阵的工作原理同8位扫描数码管类似。它有16个共阴极输出端口,每个共阴极对应有16个LED显示灯，所以其扫描译码地址需4位信号线（SEL0-SEL3），其汉字扫描码由16位段地址（0-15）输入。通过时钟的每列扫描显示完整汉字。

图2-3 LED灯红绿信号图2-4 16×16点阵LED等效电路

2.4系统设计原理

6×16扫描LED点阵只要其对应的X、Y轴顺向偏压，即可使LED发亮。例如如果想使左上角LED点亮，则Y0=1，X0=0即可。应用时限流电阻可以放在X轴或Y轴。它有16个共阴极输出端口，每个共阴极对应有16个LED显示灯。本实验就是要通过CPLD芯片产生读时序，将字形从寄存器中读出，然后产生写时序，写入16×16的点阵，使其扫描显示输出。为了显示整个汉字，首先分布好汉字的排列，以行给汉字信息；然后以128HZ的时序逐个点亮每一行，即每行逐一加高电平，根据人眼的视觉残留特性，使之形成整个汉字的

江西理工大学应用科学学院EDA课程设计

显示。

LED点阵每个点都有一个红色的发光二极管。点阵内的二极管间的连接都是行共阳，列共阴。本实验采用共阴，当二极管的共阳极为高电平，共阴极为低电平时，所接点发光；反之处于截止状态，不放光。本实验采取行扫描方式，用列给文字信息，利用周期为1s的脉冲来控制所显示的字。

本设计由32进制计数器(COUNT32)，16进制计数器(COUNT16)，行驱动（LYH）和列驱动(BBLK)组成。

图2-5 16×16点阵原理图

第三章系统子程序设计

3.1 32进制计数器设计

COUNT32.vhd是32进制的计数器，其每计一次数，输出一个字。例如当计数为“00000B”时显示“江”，当计数为“00001B”

江西理工大学应用科学学院EDA课程设计

时显示“西”。给其脉冲周期为1S。其描述如下： LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT32 IS

PORT( CLK1: IN STD_LOGIC;

QOUT : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END ENTITY COUNT32;

ARCHITECTURE BEHV OF COUNT32 IS

SIGNAL CQI : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN

PROCESS(CLK1) BEGIN

IF (CLK1'EVENT AND CLK1='1') THEN CQI<=CQI+1; END IF;

QOUT<=CQI; END PROCESS;

END ARCHITECTURE BEHV;

图3-1 CUONT32.VHD仿真波形图

江西理工大学应用科学学院EDA课程设计

图3-2 COUNT32原理图

从上图中可以看出，本模块是32进制的计数器，当CLK1给予脉冲时输出为前一个数值加1，例如：在31.46ms前输出为00110B，在这个时刻CLK1给予触发脉冲，31.46ms后的输出为00111B。可以看出该模块满足设计要求。

3.2 16进制计数器设计

COUNT16.vhd是16进制的计数器，其输出端控制行和列驱动控制器的输出数据；其描述如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT16 IS

PORT( CLK : IN STD_LOGIC;

QOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END ENTITY COUNT16;

ARCHITECTURE BEHV OF COUNT16 IS

SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK)

江西理工大学应用科学学院EDA课程设计

BEGIN

IF (CLK'EVENT AND CLK='1') THEN CQI<=CQI+1; END IF;

QOUT<=CQI; END PROCESS;

END ARCHITECTURE BEHV;

图3-3 COUNT16.vhd仿真波形图

图3-4COUNT16原理图

从上图可以看出，该模块为16进制的计数器，当CLK给予脉冲时输出为前一个数值加1，例如：在104.86ms前输出为0AH，在这个时刻CLK给予触发脉冲，104.86ms后输出值为0BH。可以看出该模块满足设计要求

江西理工大学应用科学学院EDA课程设计

3.3 列驱动设计

BBLK.vhd为列驱动控制器，该模块控制所亮的行，当输出为0001H时，给点阵的第一行高电平，输出为0010H时，给点阵的第二行高电平，依次类推，逐次给每行高电平。其描述如下： LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BBLK IS

PORT(DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); ROW : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY BBLK;

ARCHITECTURE BEHV OF BBLK IS

SIGNAL HANG : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN

PROCESS(DATAIN) BEGIN

CASE DATAIN IS

WHEN \"0000\"=> ROW<=\"1000000000000000\"; WHEN \"0001\"=> ROW<=\"0100000000000000\"; WHEN \"0010\"=> ROW<=\"0010000000000000\"; WHEN \"0011\"=> ROW<=\"0001000000000000\"; WHEN \"0100\"=> ROW<=\"0000100000000000\"; WHEN \"0101\"=> ROW<=\"0000010000000000\";

江西理工大学应用科学学院EDA课程设计

WHEN \"0110\"=> ROW<=\"0000001000000000\"; WHEN \"0111\"=> ROW<=\"0000000100000000\"; WHEN \"1000\"=> ROW<=\"0000000010000000\"; WHEN \"1001\"=> ROW<=\"0000000001000000\"; WHEN \"1010\"=> ROW<=\"0000000000100000\"; WHEN \"1011\"=> ROW<=\"0000000000010000\"; WHEN \"1100\"=> ROW<=\"0000000000001000\"; WHEN \"1101\"=> ROW<=\"0000000000000100\"; WHEN \"1110\"=> ROW<=\"0000000000000010\"; WHEN \"1111\"=> ROW<=\"0000000000000001\"; WHEN OTHERS=> ROW<=\"0000000000000000\"; END CASE;END PROCESS; END ARCHITECTURE BEHV;

江西理工大学应用科学学院EDA课程设计

图3-5 ROWCON.vhd仿真波形图

图3-6 BBLK原理图

从上图中2.621ms时刻DATATN为0010B时，输出为2000H。当DATATN为1110B时，输出为0002H。可以看出，该模块的设计满足要求。

3.4 行驱动设计

LYH.vhd为行驱动控制器DOUBT控制的是所显示的字。例如当DOUBT为00H时，表示显示第一个字；当DOUBT为01H时，表示显示第二个字，依次类推。WEI控制所显示的为字的第几行，例如

江西理工大学应用科学学院EDA课程设计

当CCK为0000B时，表示输出字的第一行文字信息；CCK为0001B时，表示输出字的第二行文字信息，依次类推。其中包括两种花样的显示方式，其描述如下： LIBRARY ieee;

USE ieee.std_logic_11.all; ENTITY LYH IS PORT( CCK : IN STD_LOGIC_VECTOR(3 downto 0); DOUBT : IN STD_LOGIC_VECTOR(4 downto 0); Q : OUT STD_LOGIC_VECTOR(15 downto 0)); END LYH;

ARCHITECTURE LYH_architecture OF LYH IS BEGIN

process(DOUBT,CCK)

variable b:std_logic_vector(15 downto 0); begin

case DOUBT is

When \"00000\"=> case CCK is

when \"0000\" =>b:=\"0100000000000000\"; when \"0001\" =>b:=\"0011000000001000\"; when \"0010\" =>b:=\"0001011111111100\"; when \"0011\" =>b:=\"0000000001000000\"; when \"0100\" =>b:=\"1000000001000000\"; when \"0101\" =>b:=\"0110000001000000\"; when \"0110\" =>b:=\"0010000001000000\"; when \"0111\" =>b:=\"0000100001000000\"; when \"1000\" =>b:=\"0001000001000000\"; when \"1001\" =>b:=\"0010000001000000\"; when \"1010\" =>b:=\"1110000001000000\"; when \"1011\" =>b:=\"0010000001000000\"; when \"1100\" =>b:=\"0010000001001000\"; when \"1101\" =>b:=\"0010111111111100\"; when \"1110\" =>b:=\"0010000000000000\";

when \"1111\" =>b:=\"0010000000000000\";

江西理工大学应用科学学院EDA课程设计

when others=>null; end case; When \"00001\"=> case CCK is

when \"0000\" =>b:=\"0000000000000000\"; when \"0001\" =>b:=\"0000000000000100\"; when \"0010\" =>b:=\"1111111111111110\"; when \"0011\" =>b:=\"0000010010000000\"; when \"0100\" =>b:=\"0000010010000000\"; when \"0101\" =>b:=\"0000010010000100\"; when \"0110\" =>b:=\"0111111111111110\"; when \"0111\" =>b:=\"0100010001000100\"; when \"1000\" =>b:=\"0100010001000100\"; when \"1001\" =>b:=\"0100010001000100\"; when \"1010\" =>b:=\"0100010001000100\"; when \"1011\" =>b:=\"0100100000110100\"; when \"1100\" =>b:=\"0101000000000100\"; when \"1101\" =>b:=\"0100000000000100\"; when \"1110\" =>b:=\"0111111111111100\"; when \"1111\" =>b:=\"0100000000000100\"; when others=>null; end case; When \"00010\"=> case CCK is

when \"0000\" =>b:=\"0000000000001000\"; when \"0001\" =>b:=\"0000011111111000\"; when \"0010\" =>b:=\"1111101001001000\"; when \"0011\" =>b:=\"0010001001001000\"; when \"0100\" =>b:=\"0010011111111100\"; when \"0101\" =>b:=\"0010001001001000\"; when \"0110\" =>b:=\"1111101001001000\"; when \"0111\" =>b:=\"0010001111111000\"; when \"1000\" =>b:=\"0010000001000000\"; when \"1001\" =>b:=\"0010000001010000\"; when \"1010\" =>b:=\"0010001111111000\"; when \"1011\" =>b:=\"0011110001000000\";

江西理工大学应用科学学院EDA课程设计

when \"1100\" =>b:=\"1110000001000000\"; when \"1101\" =>b:=\"0100000001000100\"; when \"1110\" =>b:=\"0000111111111110\";

when \"1111\" =>b:=\"0000000000000000\"; when others=>null; end case; When \"00011\"=> case CCK is

when \"0000\" =>b:=\"0000000000000000\"; when \"0001\" =>b:=\"0000000000001000\"; when \"0010\" =>b:=\"0111111111111100\"; when \"0011\" =>b:=\"0000000100000000\"; when \"0100\" =>b:=\"0000000100000000\"; when \"0101\" =>b:=\"0000000100000000\"; when \"0110\" =>b:=\"0000000100000000\"; when \"0111\" =>b:=\"0000000100000000\"; when \"1000\" =>b:=\"0000000100000000\"; when \"1001\" =>b:=\"0000000100000000\"; when \"1010\" =>b:=\"0000000100000000\"; when \"1011\" =>b:=\"0000000100000000\"; when \"1100\" =>b:=\"0000000100000100\"; when \"1101\" =>b:=\"1111111111111110\"; when \"1110\" =>b:=\"0000000000000000\";

when \"1111\" =>b:=\"0000000000000000\"; when others=>null; end case; When \"00100\"=> case CCK is

when \"0000\" =>b:=\"0000000100000000\"; when \"0001\" =>b:=\"0000000100000000\"; when \"0010\" =>b:=\"0000000100000000\"; when \"0011\" =>b:=\"0000000100000000\"; when \"0100\" =>b:=\"0000000100000100\"; when \"0101\" =>b:=\"1111111111111110\"; when \"0110\" =>b:=\"0000000100000000\"; when \"0111\" =>b:=\"0000001010000000\";

江西理工大学应用科学学院EDA课程设计

when \"1000\" =>b:=\"0000001010000000\"; when \"1001\" =>b:=\"0000001010000000\"; when \"1010\" =>b:=\"0000001001000000\"; when \"1011\" =>b:=\"0000001000010000\"; when \"1100\" =>b:=\"0000100000010000\"; when \"1101\" =>b:=\"0001000000001110\"; when \"1110\" =>b:=\"0110000000000100\";

when \"1111\" =>b:=\"0000000000000000\"; when others=>null; end case; When \"00101\"=> case CCK is

when \"0000\" =>b:=\"0010001000001000\"; when \"0001\" =>b:=\"0001000100001000\"; when \"0010\" =>b:=\"0000000000000000\"; when \"0011\" =>b:=\"0000000000100000\"; when \"0100\" =>b:=\"0111111111111110\"; when \"0101\" =>b:=\"0100000000000010\"; when \"0110\" =>b:=\"1000000000000100\"; when \"0111\" =>b:=\"0001111111100000\"; when \"1000\" =>b:=\"0000000001000000\"; when \"1001\" =>b:=\"0000000110000100\"; when \"1010\" =>b:=\"1111111111111110\"; when \"1011\" =>b:=\"0000000100000000\"; when \"1100\" =>b:=\"0000000100000000\"; when \"1101\" =>b:=\"0000000100000000\"; when \"1110\" =>b:=\"0000010100000000\";

when \"1111\" =>b:=\"0000001000000000\"; when others=>null; end case; When \"00110\"=> case CCK is

when \"0000\" =>b:=\"0000001000000000\"; when \"0001\" =>b:=\"0000000100000100\"; when \"0010\" =>b:=\"0011111111111110\"; when \"0011\" =>b:=\"0010000000000000\";

江西理工大学应用科学学院EDA课程设计

when \"0100\" =>b:=\"0010000100000100\"; when \"0101\" =>b:=\"0010100010000100\"; when \"0110\" =>b:=\"0010010010000100\"; when \"0111\" =>b:=\"0010010001001000\"; when \"1000\" =>b:=\"0010001001001000\"; when \"1001\" =>b:=\"0010001001001000\"; when \"1010\" =>b:=\"0010001000010000\"; when \"1011\" =>b:=\"0010001000010000\"; when \"1100\" =>b:=\"0010000000100000\"; when \"1101\" =>b:=\"0100000001000100\"; when \"1110\" =>b:=\"1001111111111110\";

when \"1111\" =>b:=\"1001111111111110\"; when others=>null; end case; When \"00111\"=> case CCK is

when \"0000\" =>b:=\"0000000000001000\"; when \"0001\" =>b:=\"0011111111111100\"; when \"0010\" =>b:=\"0010000100001000\"; when \"0011\" =>b:=\"0010000100001000\"; when \"0100\" =>b:=\"0010000100001000\"; when \"0101\" =>b:=\"0011111111111000\"; when \"0110\" =>b:=\"0010000100001000\"; when \"0111\" =>b:=\"0010000100001000\"; when \"1000\" =>b:=\"0010000100001000\"; when \"1001\" =>b:=\"0011111111111000\"; when \"1010\" =>b:=\"0010000100001000\"; when \"1011\" =>b:=\"0010000100001000\"; when \"1100\" =>b:=\"0010000100001000\"; when \"1101\" =>b:=\"0100000100001000\"; when \"1110\" =>b:=\"0100000100101111\";

when \"1111\" =>b:=\"1000000000010000\"; when others=>null; end case; When \"01000\"=> case CCK is

江西理工大学应用科学学院EDA课程设计

when \"0000\" =>b:=\"0000010000010000\"; when \"0001\" =>b:=\"0000111000010000\"; when \"0010\" =>b:=\"1111100010010000\"; when \"0011\" =>b:=\"0000100001010000\"; when \"0100\" =>b:=\"0000100000010000\"; when \"0101\" =>b:=\"1111111010010000\"; when \"0110\" =>b:=\"0000100001010000\"; when \"0111\" =>b:=\"0001110000010100\"; when \"1000\" =>b:=\"0001101000011110\"; when \"1001\" =>b:=\"0010100111110000\"; when \"1010\" =>b:=\"0010100000010000\"; when \"1011\" =>b:=\"0100100000010000\"; when \"1100\" =>b:=\"1000100000010000\"; when \"1101\" =>b:=\"0000100000010000\"; when \"1110\" =>b:=\"0000100000010000\";

when \"1111\" =>b:=\"0000100000010000\"; when others=>null; end case; When\"01001\"=> case CCK is

when \"0000\" =>b:=\"0010001000001000\"; when \"0001\" =>b:=\"0001000100001000\"; when \"0010\" =>b:=\"0001000100010000\"; when \"0011\" =>b:=\"0000000000100000\"; when \"0100\" =>b:=\"0111111111111110\"; when \"0101\" =>b:=\"0100000000000010\"; when \"0110\" =>b:=\"1000000000000100\"; when \"0111\" =>b:=\"0001111111100000\"; when \"1000\" =>b:=\"0000000001000000\"; when \"1001\" =>b:=\"0000000110000100\"; when \"1010\" =>b:=\"1111111111111110\"; when \"1011\" =>b:=\"0000000100000000\"; when \"1100\" =>b:=\"0000000100000000\"; when \"1101\" =>b:=\"0000000100000000\"; when \"1110\" =>b:=\"0000010100000000\";

江西理工大学应用科学学院EDA课程设计

when \"1111\" =>b:=\"0000001000000000\"; when others=>null; end case; When \"01010\"=> case CCK is

when \"0000\" =>b:=\"0000000010000000\"; when \"0001\" =>b:=\"0111100001000000\"; when \"0010\" =>b:=\"0100111111111110\"; when \"0011\" =>b:=\"0101010000000010\"; when \"0100\" =>b:=\"0101100000010100\"; when \"0101\" =>b:=\"0110001111111000\"; when \"0110\" =>b:=\"0101000000000000\"; when \"0111\" =>b:=\"0100100000001000\"; when \"1000\" =>b:=\"0100111111111100\"; when \"1001\" =>b:=\"0100100010100000\"; when \"1010\" =>b:=\"0110100010100000\";

江西理工大学应用科学学院EDA课程设计

when \"1011\" =>b:=\"0101000010100000\"; when \"1100\" =>b:=\"0100000100100010\"; when \"1101\" =>b:=\"0100000100100010\"; when \"1110\" =>b:=\"0100001000011110\";

when \"1111\" =>b:=\"0100110000000000\"; when others=>null; end case; When\"01100\"=> case CCK is

when \"0000\" =>b:=\"0000000010000000\"; when \"0001\" =>b:=\"0000000010000000\"; when \"0010\" =>b:=\"1111110010000000\"; when \"0011\" =>b:=\"0000010011111100\"; when \"0100\" =>b:=\"0100010100000100\"; when \"0101\" =>b:=\"0100011001001000\"; when \"0110\" =>b:=\"0010100001000000\"; when \"0111\" =>b:=\"0010100001000000\"; when \"1000\" =>b:=\"0001000001000000\"; when \"1001\" =>b:=\"0010100001000000\"; when \"1010\" =>b:=\"0010010010100000\"; when \"1011\" =>b:=\"0100010010100000\"; when \"1100\" =>b:=\"1000000100010000\"; when \"1101\" =>b:=\"0000000100001000\"; when \"1110\" =>b:=\"0000001000001110\";

when \"1111\" =>b:=\"0000110000000100\"; when others=>null; end case; When\"01101\"=> case CCK is

when \"0000\" =>b:=\"0000000000000000\"; when \"0001\" =>b:=\"0100000110000100\"; when \"0010\" =>b:=\"0010011001111110\"; when \"0011\" =>b:=\"0001010001000100\"; when \"0100\" =>b:=\"0000010001000100\"; when \"0101\" =>b:=\"0000010001000100\"; when \"0110\" =>b:=\"1111010001000100\";

江西理工大学应用科学学院EDA课程设计

when \"0111\" =>b:=\"0001010011000100\"; when \"1000\" =>b:=\"0001010101000100\"; when \"1001\" =>b:=\"0001011001010100\"; when \"1010\" =>b:=\"0001010001001000\"; when \"1011\" =>b:=\"0001000001000000\"; when \"1100\" =>b:=\"0001000001000000\"; when \"1101\" =>b:=\"0010100001000110\"; when \"1110\" =>b:=\"0100011111111100\";

when \"1111\" =>b:=\"0000000000000000\"; when others=>null; end case; When \"01110\"=> case CCK is

when \"0000\" =>b:=\"0000100100000000\"; when \"0001\" =>b:=\"0000100100000000\"; when \"0010\" =>b:=\"0001001111111100\"; when \"0011\" =>b:=\"0001001000001000\"; when \"0100\" =>b:=\"0011010001001000\"; when \"0101\" =>b:=\"0101100101000000\"; when \"0110\" =>b:=\"1001000101010000\"; when \"0111\" =>b:=\"0001001001001100\"; when \"1000\" =>b:=\"0001010001000100\"; when \"1001\" =>b:=\"0001000101000000\"; when \"1010\" =>b:=\"0010000100000000\"; when \"1011\" =>b:=\"0000001000000000\"; when \"1100\" =>b:=\"0101000110000100\"; when \"1101\" =>b:=\"0101000010010010\"; when \"1110\" =>b:=\"1001000000010010\";

when \"1111\" =>b:=\"0000111111111000\"; when others=>null; end case; When \"01111\"=> case CCK is

when \"0000\" =>b:=\"0000000000000000\"; when \"0001\" =>b:=\"0000000110000000\"; when \"0010\" =>b:=\"0000001111000000\";

江西理工大学应用科学学院EDA课程设计

when \"0011\" =>b:=\"0000001111000000\"; when \"0100\" =>b:=\"0000001111000000\"; when \"0101\" =>b:=\"0000001111000000\"; when \"0110\" =>b:=\"0000001111000000\"; when \"0111\" =>b:=\"0000000110000000\"; when \"1000\" =>b:=\"0000000110000000\"; when \"1001\" =>b:=\"0000000110000000\"; when \"1010\" =>b:=\"0000000000000000\"; when \"1011\" =>b:=\"0000000110000000\"; when \"1100\" =>b:=\"0000001111000000\"; when \"1101\" =>b:=\"0000000110000000\"; when \"1110\" =>b:=\"0000000000000000\";

when \"1111\" =>b:=\"0000000000000000\"; when others=>null; end case; When \"10000\"=> case CCK is

when \"0000\" =>b:=\"1011111111111111\"; when \"0001\" =>b:=\"1100111111110111\"; when \"0010\" =>b:=\"1110100000000011\"; when \"0011\" =>b:=\"1111111110111111\"; when \"0100\" =>b:=\"0111111110111111\"; when \"0101\" =>b:=\"1001111110111111\"; when \"0110\" =>b:=\"1101111110111111\"; when \"0111\" =>b:=\"1111011110111111\"; when \"1000\" =>b:=\"1110111110111111\"; when \"1001\" =>b:=\"1101111110111111\"; when \"1010\" =>b:=\"0001111110111111\"; when \"1011\" =>b:=\"1101111110111111\"; when \"1100\" =>b:=\"1101111110110111\"; when \"1101\" =>b:=\"1101000000000011\"; when \"1110\" =>b:=\"1101111111111111\";

when \"1111\" =>b:=\"1101111111111111\"; when others=>null; end case; When \"10001\"=>

江西理工大学应用科学学院EDA课程设计

case CCK is

when \"0000\" =>b:=\"1111111111111111\"; when \"0001\" =>b:=\"1111111111111011\"; when \"0010\" =>b:=\"0000000000000000\"; when \"0011\" =>b:=\"1111101101111111\"; when \"0100\" =>b:=\"1111101101111111\"; when \"0101\" =>b:=\"1111101101111011\"; when \"0110\" =>b:=\"1000000000000001\"; when \"0111\" =>b:=\"1011101110111011\"; when \"1000\" =>b:=\"1011101110111011\"; when \"1001\" =>b:=\"1011101110111011\"; when \"1010\" =>b:=\"1011101110111011\"; when \"1011\" =>b:=\"1011011111001011\"; when \"1100\" =>b:=\"1010111111111011\"; when \"1101\" =>b:=\"1011111111111011\"; when \"1110\" =>b:=\"1000000000000011\"; when \"1111\" =>b:=\"1011111111111011\"; when others=>null; end case; When \"10010\"=> case CCK is

when \"0000\" =>b:=\"1111111111110111\"; when \"0001\" =>b:=\"1111100000000111\"; when \"0010\" =>b:=\"0000010110110111\"; when \"0011\" =>b:=\"1101110110110111\"; when \"0100\" =>b:=\"1101100000000011\"; when \"0101\" =>b:=\"1101110110110111\"; when \"0110\" =>b:=\"0000010110110111\"; when \"0111\" =>b:=\"1101110000000111\"; when \"1000\" =>b:=\"1101111110111111\"; when \"1001\" =>b:=\"1101111110101111\"; when \"1010\" =>b:=\"1101110000000111\"; when \"1011\" =>b:=\"1100001110111111\"; when \"1100\" =>b:=\"0001111110111111\"; when \"1101\" =>b:=\"1011111110111011\";

江西理工大学应用科学学院EDA课程设计

when \"1110\" =>b:=\"1111000000000001\";

when \"1111\" =>b:=\"1111111111111111\"; when others=>null; end case; When \"10011\"=> case CCK is

when \"0000\" =>b:=\"1111111111111111\"; when \"0001\" =>b:=\"1111111111110111\"; when \"0010\" =>b:=\"1000000000000011\"; when \"0011\" =>b:=\"1111111011111111\"; when \"0100\" =>b:=\"1111111011111111\"; when \"0101\" =>b:=\"1111111011111111\"; when \"0110\" =>b:=\"1111111011111111\"; when \"0111\" =>b:=\"1111111011111111\"; when \"1000\" =>b:=\"1111111011111111\"; when \"1001\" =>b:=\"1111111011111111\"; when \"1010\" =>b:=\"1111111011111111\"; when \"1011\" =>b:=\"1111111011111111\"; when \"1100\" =>b:=\"1111111011111011\"; when \"1101\" =>b:=\"0000000000000000\"; when \"1110\" =>b:=\"1111111111111111\";

when \"1111\" =>b:=\"1111111111111111\"; when others=>null; end case; When \"10100\"=> case CCK is

when \"0000\" =>b:=\"1111111011111111\"; when \"0001\" =>b:=\"1111111011111111\"; when \"0010\" =>b:=\"1111111011111111\"; when \"0011\" =>b:=\"1111111011111111\"; when \"0100\" =>b:=\"1111111011111011\"; when \"0101\" =>b:=\"0000000000000001\"; when \"0110\" =>b:=\"1111111011111111\"; when \"0111\" =>b:=\"1111110101111111\"; when \"1000\" =>b:=\"1111110101111111\"; when \"1001\" =>b:=\"1111110101111111\";

江西理工大学应用科学学院EDA课程设计

when \"1010\" =>b:=\"1111110110111111\"; when \"1011\" =>b:=\"1111110111101111\"; when \"1100\" =>b:=\"1111011111101111\"; when \"1101\" =>b:=\"1110111111110001\"; when \"1110\" =>b:=\"1001111111111011\";

when \"1111\" =>b:=\"1111111111111111\"; when others=>null; end case; When \"10101\"=> case CCK is

when \"0000\" =>b:=\"1101110111110111\"; when \"0001\" =>b:=\"1110111011110111\"; when \"0010\" =>b:=\"1111111111111111\"; when \"0011\" =>b:=\"1111111111011111\"; when \"0100\" =>b:=\"1000000000000001\"; when \"0101\" =>b:=\"1011111111111101\"; when \"0110\" =>b:=\"0111111111111011\"; when \"0111\" =>b:=\"1110000000011111\"; when \"1000\" =>b:=\"1111111110111111\"; when \"1001\" =>b:=\"1111111001111011\"; when \"1010\" =>b:=\"0000000000000001\"; when \"1011\" =>b:=\"1111111011111111\"; when \"1100\" =>b:=\"1111111011111111\"; when \"1101\" =>b:=\"1111111011111111\"; when \"1110\" =>b:=\"1111101011111111\";

when \"1111\" =>b:=\"1111110111111111\"; when others=>null; end case; When \"10110\"=> case CCK is

when \"0000\" =>b:=\"1111110111111111\"; when \"0001\" =>b:=\"1111111011111011\"; when \"0010\" =>b:=\"1100000000000001\"; when \"0011\" =>b:=\"1101111111111111\"; when \"0100\" =>b:=\"1101111011111011\"; when \"0101\" =>b:=\"1101011101111011\";

江西理工大学应用科学学院EDA课程设计

when \"0110\" =>b:=\"1101101101111011\"; when \"0111\" =>b:=\"1101101110110111\"; when \"1000\" =>b:=\"1101110110110111\"; when \"1001\" =>b:=\"1101110110110111\"; when \"1010\" =>b:=\"1101110111101111\"; when \"1011\" =>b:=\"1101110111101111\"; when \"1100\" =>b:=\"1101111111011111\"; when \"1101\" =>b:=\"1011111110111011\"; when \"1110\" =>b:=\"0110000000000001\";

when \"1111\" =>b:=\"0110000000000001\"; when others=>null; end case; When \"10111\"=> case CCK is

when \"0000\" =>b:=\"1111111111110111\"; when \"0001\" =>b:=\"1100000000000011\"; when \"0010\" =>b:=\"1101111011110111\"; when \"0011\" =>b:=\"1101111011110111\"; when \"0100\" =>b:=\"1101111011110111\"; when \"0101\" =>b:=\"1100000000000111\"; when \"0110\" =>b:=\"1101111011110111\"; when \"0111\" =>b:=\"1101111011110111\"; when \"1000\" =>b:=\"1101111011110111\"; when \"1001\" =>b:=\"1100000000000111\"; when \"1010\" =>b:=\"1101111011110111\"; when \"1011\" =>b:=\"1101111011110111\"; when \"1100\" =>b:=\"1101111011110111\"; when \"1101\" =>b:=\"1011111011110111\"; when \"1110\" =>b:=\"1011111011010000\";

when \"1111\" =>b:=\"0111111111101111\"; when others=>null; end case; When \"11000\"=> case CCK is

when \"0000\" =>b:=\"1111101111101111\"; when \"0001\" =>b:=\"1111000111101111\";

江西理工大学应用科学学院EDA课程设计

when \"0010\" =>b:=\"0000011101101111\"; when \"0011\" =>b:=\"1111011110101111\"; when \"0100\" =>b:=\"1111011111101111\"; when \"0101\" =>b:=\"0000000101101111\"; when \"0110\" =>b:=\"1111011110101111\"; when \"0111\" =>b:=\"1110001111101011\"; when \"1000\" =>b:=\"1110010111100001\"; when \"1001\" =>b:=\"1101011000001111\"; when \"1010\" =>b:=\"1101011111101111\"; when \"1011\" =>b:=\"1011011111101111\"; when \"1100\" =>b:=\"0111011111101111\"; when \"1101\" =>b:=\"1111011111101111\"; when \"1110\" =>b:=\"1111011111101111\";

when \"1111\" =>b:=\"1111011111101111\"; when others=>null; end case; When \"11001\"=> case CCK is

when \"0000\" =>b:=\"1101110111110111\"; when \"0001\" =>b:=\"1110111011110111\"; when \"0010\" =>b:=\"1110111011101111\"; when \"0011\" =>b:=\"1111111111011111\"; when \"0100\" =>b:=\"1000000000000001\"; when \"0101\" =>b:=\"1011111111111101\"; when \"0110\" =>b:=\"0111111111111011\"; when \"0111\" =>b:=\"1110000000011111\"; when \"1000\" =>b:=\"1111111110111111\"; when \"1001\" =>b:=\"1111111001111011\"; when \"1010\" =>b:=\"0000000000000001\"; when \"1011\" =>b:=\"1111111011111111\"; when \"1100\" =>b:=\"1111111011111111\"; when \"1101\" =>b:=\"1111111011111111\"; when \"1110\" =>b:=\"1111101011111111\";

when \"1111\" =>b:=\"1111110111111111\"; when others=>null; end case;

江西理工大学应用科学学院EDA课程设计

When\"11010\"=> case CCK is

when \"0000\" =>b:=\"1111111101111111\"; when \"0001\" =>b:=\"1000011110111111\"; when \"0010\" =>b:=\"1011000000000001\"; when \"0011\" =>b:=\"1010101111111101\"; when \"0100\" =>b:=\"1010011111101011\"; when \"0101\" =>b:=\"1001110000000111\"; when \"0110\" =>b:=\"1010111111111111\"; when \"0111\" =>b:=\"1011011111110111\"; when \"1000\" =>b:=\"1011000000000011\"; when \"1001\" =>b:=\"1011011101011111\"; when \"1010\" =>b:=\"1001011101011111\"; when \"1011\" =>b:=\"1010111101011111\"; when \"1100\" =>b:=\"1011111011011101\";

江西理工大学应用科学学院EDA课程设计

when \"1101\" =>b:=\"1011111011011101\"; when \"1110\" =>b:=\"1011110111100001\";

when \"1111\" =>b:=\"1011001111111111\"; when others=>null; end case; When \"11100\"=> case CCK is

when \"0000\" =>b:=\"1111111101111111\"; when \"0001\" =>b:=\"1111111101111111\"; when \"0010\" =>b:=\"0000001101111111\"; when \"0011\" =>b:=\"1111101100000011\"; when \"0100\" =>b:=\"1011101011111011\"; when \"0101\" =>b:=\"1011100110110111\"; when \"0110\" =>b:=\"1101011110111111\"; when \"0111\" =>b:=\"1101011110111111\"; when \"1000\" =>b:=\"1110111110111111\"; when \"1001\" =>b:=\"1101011110111111\"; when \"1010\" =>b:=\"1101101101011111\"; when \"1011\" =>b:=\"1011101101011111\"; when \"1100\" =>b:=\"0111111011101111\"; when \"1101\" =>b:=\"1111111011110111\"; when \"1110\" =>b:=\"1111110111110001\";

when \"1111\" =>b:=\"1111001111111011\"; when others=>null; end case; When \"11101\"=> case CCK is

WHEN\"0000\" =>b:=\"1111111111111111\"; when \"0001\" =>b:=\"1011111001111011\"; when \"0010\" =>b:=\"1101100110000001\"; when \"0011\" =>b:=\"1110101110111011\"; when \"0100\" =>b:=\"1111101110111011\"; when \"0101\" =>b:=\"1111101110111011\"; when \"0110\" =>b:=\"0000101110111011\"; when \"0111\" =>b:=\"1110101100111011\"; when \"1000\" =>b:=\"1110101010111011\";

江西理工大学应用科学学院EDA课程设计

when \"1001\" =>b:=\"1110100110101011\"; when \"1010\" =>b:=\"1110101110110111\"; when \"1011\" =>b:=\"1110111110111111\"; when \"1100\" =>b:=\"1110111110111111\"; when \"1101\" =>b:=\"1101011110111001\"; when \"1110\" =>b:=\"1011100000000011\";

when \"1111\" =>b:=\"1111111111111111\"; when others=>null; end case; When \"11110\"=> case CCK is

when \"0000\" =>b:=\"1111011011111111\"; when \"0001\" =>b:=\"1111011011111111\"; when \"0010\" =>b:=\"1110110000000011\"; when \"0011\" =>b:=\"1110110111110111\"; when \"0100\" =>b:=\"1100101110110111\"; when \"0101\" =>b:=\"1010011010111111\"; when \"0110\" =>b:=\"0110111010101111\"; when \"0111\" =>b:=\"1110110110110011\"; when \"1000\" =>b:=\"1110101110111011\"; when \"1001\" =>b:=\"1110111010111111\"; when \"1010\" =>b:=\"1101111011111111\"; when \"1011\" =>b:=\"1111110111111111\"; when \"1100\" =>b:=\"1010111001111011\"; when \"1101\" =>b:=\"1010111101101101\"; when \"1110\" =>b:=\"0110111111101101\";

when \"1111\" =>b:=\"1111000000000111\"; when others=>null; end case; When \"11111\"=> case CCK is

when \"0000\" =>b:=\"1111111111111111\"; when \"0001\" =>b:=\"1111111001111111\"; when \"0010\" =>b:=\"1111110000111111\"; when \"0011\" =>b:=\"1111110000111111\"; when \"0100\" =>b:=\"1111110000111111\";

江西理工大学应用科学学院EDA课程设计

when \"0101\" =>b:=\"1111110000111111\"; when \"0110\" =>b:=\"1111110000111111\"; when \"0111\" =>b:=\"1111111001111111\"; when \"1000\" =>b:=\"1111111001111111\"; when \"1001\" =>b:=\"1111111001111111\"; when \"1010\" =>b:=\"1111111111111111\"; when \"1011\" =>b:=\"1111111001111111\"; when \"1100\" =>b:=\"1111110000111111\"; when \"1101\" =>b:=\"1111111001111111\"; when \"1110\" =>b:=\"1111111111111111\";

when \"1111\" =>b:=\"1111111111111111\"; when others=>null; end case; when others=>null; end case; q<=b;

end process;

ENDLYH_architecture;

江西理工大学应用科学学院EDA课程设计

图3-7vhd仿真波形图

图3-8行驱动原理图

在上图中，当DOUBT为05H，CCK为1011时，输出为0100H,表示输出是第1个字，第3行的文字信息；当DOUBT为07H，CCK为0000B时，输出为0008H，表示输出是第7个文字，第1行的文字信息。将仿真图的输出结果和原程

江西理工大学应用科学学院EDA课程设计

第四章原理图仿真波形

将上述模块连接起来组成原理图，进行编译仿真。

江西理工大学应用科学学院EDA课程设计

图4-1 原理图仿真时序图

上图中， CLK1为0，表示此时显示的是第1个字。输出Q为0040H，ROW为1000H，此时输出的是第1个字的第1行文字信息；当Q输出为8040H，ROW输出为0800H，此时输出的是第1个字的第2行文字信息，依次类推，逐渐点亮16行，第1个字显示出来。当CLK给周期为1S的脉冲时，将依次显示文字。

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