AM29LV065D

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both AdvancedMicro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD andFujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Anychanges that have been made are the result of normal datasheet improvement and are noted in thedocument revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To orderthese products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansionmemory solutions.

Publication Number 234 Revision BAmendment 0 Issue Date January 10, 2002

Am29LV065D

Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only

UniformSectorFlash Memory with VersatileIOTM Control

DISTINCTIVE CHARACTERISTICS

sSingle power supply operation

—3.0 to 3.6 volt read, erase, and program operationssVersatileIOTM control

—Device generates output voltages and tolerates input

voltages on the DQ I/Os as determined by the voltage on VIO inputsHigh performance

—Access times as fast as 90 ns

sManufactured on 0.23 µm process technologysCFI (Common Flash Interface) compliant

—Provides device-specific information to the system,

allowing host software to easily reconfigure for different Flash devicessSecSi (Secured Silicon) Sector region

—256-byte sector for permanent, secure identification

through an 16-byte random Electronic Serial Number—May be programmed and locked at the factory or by

the customer

—Accessible through a command sequencesUltra low power consumption (typical values at 3.0 V,

5 MHz)

—9 mA typical active read current

—26 mA typical erase/program current—200 nA typical standby mode currentsFlexible sector architecture

—One hundred twenty-eight Kbyte sectors

sSector Protection

—A hardware method to lock a sector to prevent

program or erase operations within that sector

—Sectors can be locked in-system or via programming

equipment

—Temporary Sector Unprotect feature allows code

changes in previously locked sectorssEmbedded Algorithms

—Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes

and verifies data at specified addresses

sCompatibility with JEDEC standards

—Pinout and software compatible with single-power

supply Flash

—Superior inadvertent write protectionsMinimum 1 million erase cycle guarantee per sector sPackage options

—48-pin TSOP (standard or reverse pinout)—63-ball FBGA

sErase Suspend/Erase Resume

—Suspends an erase operation to read data from, or

program data to, a sector that is not being erased, then resumes the erase operationsData# Polling and toggle bits

—Provides a software method of detecting program or

erase operation completionsUnlock Bypass Program command

—Reduces overall programming time when issuing

multiple program command sequencessReady/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or

erase cycle completionsHardware reset pin (RESET#)

—Hardware method to reset the device for reading array

datasACC pin

—Accelerates programming time for higher throughput

during system productionsProgram and Erase Performance (VHH not applied to

the ACC input pin)

—Byte program time: 5 µs typical

—Sector erase time: 0.9 s typical for each Kbyte

sectors20-year data retention at 125°C

—Reliable operation for the life of the system

Publication# 234Rev: BAmendment/0Issue Date: January 10, 2002

RefertoAMD’sWebsite(www.amd.com)forthelatestinformation.

GENERAL DESCRIPTION

The Am29LV065D is a Mbit, 3.0 Volt (3.0 V to 3.6V) single power supply flash memory devices orga-nized as 8,388,608 bytes. Data appears on DQ0-DQ7.The device is designed to be programmed in-systemwith the standard system 3.0 volt VCC supply. A 12.0volt VPP is not required for program or erase opera-tions. The device can also be programmed in standardEPROM programmers.

The device offers access times of 90, 100, and 120 ns.The device is offered in standard or reverse 48-pinTSOP and 63-ball FBGA packages. To eliminate buscontention each device has separate chip enable(CE#), write enable (WE#) and output enable (OE#)controls.

Each device requires only a single 3.0 Volt powersupply (3.0 V to 3.6 V) for both read and write func-tions. Internally generated and regulated voltages areprovided for the program and erase operations. The device is entirely command set compatible withthe JEDEC single-power-supply Flash standard.Commands are written to the command register usingstandard microprocessor write timing. Register con-tents serve as inputs to an internal state-machine thatcontrols the erase and programming circuitry. Writecycles also internally latch addresses and dataneeded for the programming and erase operations.Reading data out of the device is similar to readingfrom other Flash or EPROM devices.

Device programming occurs by executing the programcommand sequence. This initiates the EmbeddedProgram algorithm—an internal algorithm that auto-matically times the program pulse widths and verifiesproper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only twowrite cycles to program data instead of four.

Device erasure occurs by executing the erase com-mand sequence. This initiates the Embedded Erasealgorithm—an internal algorithm that automaticallypreprograms the array (if it is not already pro-grammed) before executing the erase operation. Dur-ing erase, the device automatically times the erasepulse widths and verifies proper cell margin.

The VersatileIO™ (VIO) control allows the host systemto set the voltage levels that the device generates andtolerates on CE# and DQ I/Os to the same voltagelevel that is asserted on VIO. VIO is available in twoconfigurations (1.8–2.9 V and 3.0–5.0 V) for operationin various system environments.

The host system can detect whether a program orerase operation is complete by observing the RY/BY#

pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-gle) status bits. After a program or erase cycle hasbeen completed, the device is ready to read array dataor accept another command.

The sector erase architecture allows memory sec-tors to be erased and reprogrammed without affectingthe data contents of other sectors. The device is fullyerased when shipped from the factory.

Hardware data protection measures include a lowVCC detector that automatically inhibits write opera-tions during power transitions. The hardware sectorprotection feature disables both program and eraseoperations in any combination of sectors of memory.This can be achieved in-system or via programmingequipment.

The Erase Suspend/Erase Resume feature enablesthe user to put erase on hold for any period of time toread data from, or program data to, any sector that isnot selected for erasure. True background erase canthus be achieved.

The hardware RESET# pin terminates any operationin progress and resets the internal state machine toreading array data. The RESET# pin may be tied tothe system reset circuitry. A system reset would thusalso reset the device, enabling the system micropro-cessor to read boot-up firmware from the Flash mem-ory device.

The device offers a standby mode as a power-savingfeature. Once the system places the device into thestandby mode power consumption is greatly reduced.The SecSiTM (Secured Silicon) Sector provides anminimum 256-byte area for code or data that can bepermanently protected. Once this sector is protected,no further programming or erasing within the sectorcan occur.

The accelerated program (ACC) feature allows thesystem to program the device at a much faster rate.When ACC is pulled high to VHH, the device enters theUnlock Bypass mode, enabling the user to reduce thetime needed to do the program operation. This featureis intended to increase factory throughput during sys-tem production, but may also be used in the field if de-sired.

AMD’s Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability and cost effective-ness. The device electrically erases all bits within asector simultaneously via Fowler-Nordheim tunnelling.The data is programmed using hot electron injection.

2Am29LV065DJanuary 10, 2002

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9

Table 1. Am29LV065D Device Bus Operations ................................9

Figure 6. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ...................................................................30Reading Toggle Bits DQ6/DQ2 ...............................................30DQ5: Exceeded Timing Limits ................................................30DQ3: Sector Erase Timer .......................................................30

Table 11. Write Operation Status ...................................................31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative OvershootWaveform..................... 32Figure 8. Maximum Positive OvershootWaveform....................... 32

VersatileIOTM (VIO) Control ........................................................9Requirements for Reading Array Data .....................................9Writing Commands/Command Sequences ............................10Accelerated Program Operation .............................................10Autoselect Functions ..............................................................10Standby Mode ........................................................................10Automatic Sleep Mode ...........................................................10RESET#: Hardware Reset Pin ...............................................10Output Disable Mode ..............................................................11

Table 2. Sector Address Table ........................................................11

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 32DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. ICC1 Current vs. Time (Showing Active and

AutomaticSleepCurrents)............................................................. 34Figure 10. Typical ICC1 vs. Frequency............................................ 34Figure 11. Test Setup.................................................................... 35Table 12. Test Specifications .........................................................35Figure 12. Input Waveforms and MeasurementLevels................. 35

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Autoselect Mode .....................................................................15

Table 3. Am29LV065D Autoselect Codes, (HighVoltageMethod) 15

Sector Group Protection and Unprotection .............................16

Table 4. Sector Group Protection/Unprotection AddressTable .....16

Key to Switching Waveforms. . . . . . . . . . . . . . . . 35AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36Read-Only Operations ...........................................................36

Figure 13. Read Operation Timings............................................... 36

Temporary Sector Group Unprotect .......................................17

Figure 1. Temporary Sector Group UnprotectOperation................ 17Figure 2. In-System Sector Group Protect/UnprotectAlgorithms... 18

Hardware Reset (RESET#) ....................................................37

Figure 14. Reset Timings............................................................... 37

Erase and Program Operations ..............................................38

Figure 15. Program Operation Timings.......................................... 39Figure 16. Accelerated Program Timing Diagram.......................... 39Figure 17. Chip/Sector Erase Operation Timings.......................... 40Figure 18. Data# Polling Timings (DuringEmbeddedAlgorithms). 41Figure 19. Toggle Bit Timings (DuringEmbeddedAlgorithms)...... 42Figure 20. DQ2 vs. DQ6................................................................. 42

SecSi (Secured Silicon) Sector Flash MemoryRegion ..........19

Table 5. SecSi Sector Contents ......................................................19

Hardware Data Protection ......................................................19Low VCC Write Inhibit ............................................................19Write Pulse “Glitch” Protection ...............................................20Logical Inhibit ..........................................................................20Power-Up Write Inhibit ............................................................20Common Flash Memory Interface (CFI). . . . . . . 20

Table 6. CFI Query Identification String.......................................... 20System Interface String................................................................... 21Table 8. Device Geometry Definition.............................................. 21Table 9. Primary Vendor-Specific Extended Query........................ 22

Temporary Sector Unprotect ..................................................43

Figure 21. Temporary Sector Group UnprotectTimingDiagram... 43Figure 22. Sector Group Protect and UnprotectTimingDiagram.. 44Figure 23. Alternate CE# Controlled Write

(Erase/Program)OperationTimings.............................................. 46

Command Definitions . . . . . . . . . . . . . . . . . . . . . 22Reading Array Data ................................................................22Reset Command .....................................................................23Autoselect Command Sequence ............................................23Enter SecSi Sector/Exit SecSi Sector

CommandSequence ..............................................................23Byte Program Command Sequence .......................................23Unlock Bypass Command Sequence .....................................24

Figure 3. Program Operation.......................................................... 24

Chip Erase Command Sequence ...........................................24Sector Erase Command Sequence ........................................25Erase Suspend/Erase Resume Commands ...........................25

Figure 4. Erase Operation............................................................... 26

Command Definitions .............................................................27

Table 10. Am29LV065D Command Definitions ..............................27

Write Operation Status . . . . . . . . . . . . . . . . . . . . .28DQ7: Data# Polling .................................................................28

Figure 5. Data# Polling Algorithm................................................... 28

RY/BY#: Ready/Busy# ...........................................................29DQ6: Toggle Bit I ....................................................................29

Erase And Programming Performance . . . . . . . 47Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 47TSOP Pin Capacitance. . . . . . . . . . . . . . . . . . . . . 47Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48TS 048—48-Pin Standard Pinout Thin Small Outline

Package(TSOP) .....................................................................48TSR048—48-Pin Reverse Pinout Thin Small Outline

Package(TSOP) .....................................................................49FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)

11 x 12 mm package ..............................................................50Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 51Revision A (July 27, 2000) ......................................................51Revision A+1 (August 4, 2000) ...............................................51Revision A+2 (August 14, 2000) .............................................51Revision A+3 (August 25, 2000) .............................................51Revision A+4 (October 19, 2000) ...........................................51Revision A+5 (November 7, 2000) .........................................51Revision A+6 (November 27, 2000) .......................................51Revision A+7 (March 8, 2001) ................................................51Revision B (January 10, 2002) ...............................................51

January 10, 2002Am29LV065D3

PRODUCT SELECTOR GUIDE

Part NumberSpeed OptionMax Access Time (ns)CE# Access Time (ns)OE# Access Time (ns)

Note: See “AC Characteristics” for full specifications.

VCC = 3.0–3.6 V, VIO = 3.0–5.0 VVCC = 3.0–3.6 V, VIO = 1.8–2.9 V

90903590R

101R10010035Am29LV065D

120R121R12012050

BLOCK DIAGRAM

RY/BY#

VCCVSS

RESET#

Sector SwitchesErase VoltageGenerator

VIO

Input/OutputBuffersDQ0–DQ7

WE#ACC

StateControlCommandRegister

PGM VoltageGenerator

Chip EnableOutput Enable

Logic

STB

DataLatch

CE#OE#

STB

VCC Detector

Timer

Address LatchY-DecoderY-Gating

X-Decoder

Cell Matrix

A0–A22

4Am29LV065DJanuary 10, 2002

CONNECTION DIAGRAMS

NCA22A16A15A14A13A12A11A9A8WE#RESET#ACCRY/BY#A18A7A6A5A4A3A2A1NCNC123456710111213141516171819202122232448-Pin Standard TSOP48474443424140393837363534333231302928272625NCNCA17VSSA20A19A10DQ7DQ6DQ5DQ4VCCVIOA21DQ3DQ2DQ1DQ0OE#VSSCE#A0NCNCNCNCA17VSSA20A19A10DQ7DQ6DQ5DQ4VCCVIOA21DQ3DQ2DQ1DQ0OE#VSSCE#A0NCNC123456710111213141516171819202122232448-Pin Reverse TSOP48474443424140393837363534333231302928272625NCA22A16A15A14A13A12A11A9A8WE#RESET#ACCRY/BY#A18A7A6A5A4A3A2A1NCNCJanuary 10, 2002Am29LV065D5

CONNECTION DIAGRAMS

63-Ball FBGA

Top View, Balls Facing DownA8NC*A7NC*B8NC*B7NC*C7A14C6A9C5WE#C4RY/BY#C3A7D7A13D6A8D5RESET#D4ACCD3A18D2A4E7A15E6A11E5A22E4NCE3A6E2A2F7A16F6A12F5NCF4NCF3A5F2A1G7A17G6A19G5DQ5G4DQ2G3DQ0G2A0H7NCH6A10H5NCH4DQ3H3NCH2CE#J7A20J6DQ6J5VCCJ4VIOJ3NCJ2OE#K7VSSK6DQ7K5DQ4K4A21K3DQ1K2VSSL8NC*L7NC*M8NC*M7NC*A2NC*A1NC*B1NC*C2A3L2NC*L1M2NC*M1NC** Balls are shorted together via the substrate but not connected to the die.NC*Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory productsin FBGA packages.

Flash memory devices in FBGA packages may bedamaged if exposed to ultrasonic cleaning methods.The package and/or data integrity may be compromisedif the package body is exposed to temperatures above150°C for prolonged periods of time.

6Am29LV065DJanuary 10, 2002

PIN DESCRIPTION

A0–A22DQ0–DQ7CE#OE#WE#ACCRESET#RY/BY#VCC

=23 Addresses inputs=8 Data inputs/outputs=Chip Enable input=Output Enable input=Write Enable input=Acceleration Input=Hardware Reset Pin input=Ready/Busy output

=3.0 volt-only single power supply(see Product Selector Guide for speedoptions and voltage supplytolerances)=Output Buffer power=Device Ground

=Pin Not Connected Internally

LOGIC SYMBOL

23

A0–A22CE# OE#WE#ACCRESET#

RY/BY#

VIO

DQ0–DQ7

8

VIO VSSNC

January 10, 2002Am29LV065D7

ORDERING INFORMATIONStandard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) isformed by a combination of the following:Am29LV065D

U

90R

WH

I

N

OPTIONAL PROCESSING

Blank=Standard ProcessingN=16-byte ESN devices

(Contact an AMD representative for more information)TEMPERATURE RANGEI = Industrial (–40°C to +85°C)E =Extended (–55°C to +125°C)

PACKAGE TYPEE=48-Pin Standard Pinout Thin Small Outline Package (TS 048)F=48-Pin Reverse Pinout Thin Small Outline Package (TSR048)WH=63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 11 x 12 mm package (FBE063)SPEED OPTION

See Product Selector Guide and Valid CombinationsSECTOR ARCHITECTUREU=Uniform sector device

DEVICE NUMBER/DESCRIPTION

Am29LV065D

Megabit (8 M x 8-Bit) CMOS Uniform Sector Flash Memory with VersatileIO Control3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP

PackagesAM29LV065DU90R,AM29LV065DU90RAM29LV065DU101R,AM29LV065DU101RAM29LV065DU120R,AM29LV065DU120RAM29LV065DU121R,AM29LV065DU121R

Valid Combinations for FBGA Packages

Speed/VIO Range90ns,

VIO = 3.0 V – 5.0 V100 ns,

VIO = 1.8 V – 2.9 V120 ns,

VIO = 3.0 V – 5.0 V120 ns,

VIO = 1.8 V – 2.9 V

Order NumberAM29LV065DU90R

WHI

AM29LV065DU101RAM29LV065DU120R

L065DU01RL065DU12RPackage MarkingL065DU90R

I

Speed/VIO Range

90 ns, VIO = 3.0 V – 5.0 V100 ns, VIO = 1.8 V – 2.9 V

EI, FI

EI, EE,FI, FE

120 ns, VIO =

WHI, I, 3.0 V – 5.0 VWHEE120 ns, VIO =

AM29LV065DU121RL065DU21R

1.8 V – 2.9 V

Valid Combinations

Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.

8Am29LV065DJanuary 10, 2002

DEVICE BUS OPERATIONS

This section describes the requirements and use ofthe device bus operations, which are initiated throughthe internal command register. The command registeritself does not occupy any addressable memory loca-tion. The register is a latch used to store the com-mands, along with the address and data informationneeded to execute the command. The contents of the

Table 1.

Operation

Read

Write (Program/Erase)Accelerated ProgramStandbyOutput DisableReset

Sector Group Protect (Note 2)Sector Group Unprotect (Note 2)

Temporary Sector Group Unprotect

CE#LLLVCC ± 0.3 VLXLLX

register serve as inputs to the internal state machine.The state machine outputs dictate the function of thedevice. Table 1 lists the device bus operations, the in-puts and control levels they require, and the resultingoutput. The following subsections describe each ofthese operations in further detail.

Am29LV065D Device Bus Operations

WE#HLLXHXLLX

RESET#

HHHVCC ± 0.3 VHLVIDVIDVID

ACC

Addresses(Note 2)

AINAINAINXXXSA, A6 = L, A1 = H, A0 = LSA, A6 = H, A1 = H, A0 = L

AIN

DQ0–DQ7DOUT(Note 4)(Note 4)High-ZHigh-ZHigh-Z(Note 4)(Note 4)(Note 4)

OE#LHHXHXHHX

XXVHHHXXXXX

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:

1.Addresses are A22:A0. Sector addresses are A22:A16.

2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

3.All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version

ordered.)

4.DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

VersatileIOTM (VIO) Control

The VersatileIO™ (VIO) control allows the host systemto set the voltage levels that the device generates andtolerates on CE# and DQ I/Os to the same voltagelevel that is asserted on VIO. VIO is available in twoconfigurations (1.8–2.9 V and 3.0–5.0 V) for operationin various system environments.

For example, a VI/O of 4.5–5.0 volts allows for I/O atthe 5 volt level, driving and receiving signals to andfrom other 5 V devices on the same data bus.

Requirements for Reading Array Data

To read array data from the outputs, the system mustdrive the CE# and OE# pins to VIL. CE# is the powercontrol and selects the device. OE# is the output con-trol and gates array data to the output pins. WE#should remain at VIH.

The internal state machine is set for reading array dataupon device power-up, or after a hardware reset. Thisensures that no spurious alteration of the memorycontent occurs during the power transition. No com-mand is necessary in this mode to obtain array data.Standard microprocessor read cycles that assert validaddresses on the device address inputs produce validdata on the device data outputs. The device remains

January 10, 2002Am29LV065D9

enabled for read access until the command registercontents are altered.

See “VersatileIO (VIO) Control” for more information.Refer to the AC Read-Only Operations table for timingspecifications and to Figure 13 for the timing diagram.ICC1 in the DC Characteristics table represents the ac-tive current specification for reading array data.

TM

Standby Mode

When the system is not reading or writing to the de-vice, it can place the device in the standby mode. Inthis mode, current consumption is greatly reduced,and the outputs are placed in the high impedancestate, independent of the OE# input.

The device enters the CMOS standby mode when theCE# and RESET# pins are both held at VCC ± 0.3 V.(Note that this is a more restricted voltage range thanVIH.) If CE# and RESET# are held at VIH, but not withinVCC ± 0.3 V, the device will be in the standby mode,but the standby current will be greater. The device re-quires standard access time (tCE) for read accesswhen the device is in either of these standby modes,before it is ready to read data.

If the device is deselected during erasure or program-ming, the device draws active current until theoperation is completed.

ICC3 in the DC Characteristics table represents thestandby current specification.

Writing Commands/Command Sequences

To write a command or command sequence (which in-cludes programming data to the device and erasingsectors of memory), the system must drive WE# andCE# to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facil-itate faster programming. Once the device enters theUnlock Bypass mode, only two write cycles are re-quired to program a byte, instead of four. The “ByteProgram Command Sequence” section has details onprogramming data to the device using both standardand Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-tors, or the entire device. Table 2 indicates the addressspace that each sector occupies.

ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The ACCharacteristics section contains timing specificationtables and timing diagrams for write operations.Accelerated Program Operation

The device offers accelerated program operationsthrough the ACC function. This function is primarily in-tended to allow faster manufacturing throughput dur-ing system production.

If the system asserts VHH on this pin, the device auto-matically enters the aforementioned Unlock Bypassmode, temporarily unprotects any protected sectors,and uses the higher voltage on the pin to reduce thetime required for program operations. The systemwould use a two-cycle program command sequenceas required by the Unlock Bypass mode. RemovingVHH from the ACC pin returns the device to normal op-eration. Note that the ACC pin must not be at VHH foroperations other than accelerated programming, ordevice damage may result.Autoselect Functions

If the system writes the autoselect command se-quence, the device enters the autoselect mode. Thesystem can then read autoselect codes from the inter-nal register (which is separate from the memory array)on DQ7–DQ0. Standard read cycle timings apply inthis mode. Refer to the Autoselect Mode and Autose-lect Command Sequence sections for more informa-tion.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-ergy consumption. The device automatically enablesthis mode when addresses remain stable for tACC +30ns. The automatic sleep mode is independent ofthe CE#, WE#, and OE# control signals. Standard ad-dress access timings provide new data when ad-dresses are changed. While in sleep mode, outputdata is latched and always available to the system.ICC4 in the DC Characteristics table represents theautomatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-setting the device to reading array data. When the RE-SET# pin is driven low for at least a period of tRP, thedevice immediately terminates any operation inprogress, tristates all output pins, and ignores allread/write commands for the duration of the RESET#pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device isready to accept another command sequence, to en-sure data integrity.

Current is reduced for the duration of the RESET#pulse. When RESET# is held at VSS±0.3 V, the devicedraws CMOS standby current (ICC4). If RESET# is heldat VIL but not within VSS±0.3 V, the standby current willbe greater.

The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flashmemory, enabling the system to read the boot-up firm-ware from the Flash memory.

10Am29LV065DJanuary 10, 2002

If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until theinternal reset operation is complete, which requires atime of tREADY (during Embedded Algorithms). Thesystem can thus monitor RY/BY# to determine0whether the reset operation is complete. If RESET# is01

asserted when a program or erase operation is not eytBT󰀀/F.2(s)tTJ󰀀0 -1.2083 TD󰀀0.0067muiomdurY/BB# pi7( c)6.7(o1 1 Tf󰀀15.

January 10, 2002Am29LV065D11

Table 2.

SectorSA27SA28SA29SA30SA31SA32SA33SA34SA35SA36SA37SA38SA39SA40SA41SA42SA43SA44SA45SA46SA47SA48SA49SA50SA51SA52SA53SASA55SA56SA57SA58SA59SA60SA61

A2200000000000000000000000000000000000

A2100000111111111111111111111111111111

A2011111000000000000000011111111111111

Sector Address Table (Continued)

A1911111000000001111111100000000111111

A1801111000011110000111100001111000011

A1710011001100110011001100110011001100

A1610101010101010101010101010101010101

8-bit Address Range(in hexadecimal)1B0000–1BFFFF1C0000–1CFFFF1D0000–1DFFFF1E0000–1EFFFF1F0000–1FFFFF200000–20FFFF210000–21FFFF220000–22FFFF230000–23FFFF240000–24FFFF250000–25FFFF260000–26FFFF270000–27FFFF280000–28FFFF290000–29FFFF2A0000–2AFFFF2B0000–2BFFFF2C0000–2CFFFF2D0000–2DFFFF2E0000–2EFFFF2F0000–2FFFFF300000–30FFFF310000–31FFFF320000–32FFFF330000–33FFFF340000–34FFFF350000–35FFFF360000–36FFFF370000–37FFFF380000–38FFFF390000–39FFFF3A0000–3AFFFF3B0000–3BFFFF3C0000–3CFFFF3D0000–3DFFFF

12Am29LV065DJanuary 10, 2002

Table 2.

SectorSA62SA63SASA65SA66SA67SA68SA69SA70SA71SA72SA73SA74SA75SA76SA77SA78SA79SA80SA81SA82SA83SA84SA85SA86SA87SA88SASA90SA91SA92SA93SA94SA95SA96

A2200111111111111111111111111111111111

A2111000000000000000000000000000000001

A2011000000000000000011111111111111110

Sector Address Table (Continued)

A1911000000001111111100000000111111110

A1811000011110000111100001111000011110

A1711001100110011001100110011001100110

A1601010101010101010101010101010101010

8-bit Address Range(in hexadecimal)3E0000–3EFFFF3F0000–3FFFFF400000–40FFFF410000–41FFFF420000–42FFFF430000–43FFFF440000–44FFFF450000–45FFFF460000–46FFFF470000–47FFFF480000–48FFFF490000–49FFFF4A0000–4AFFFF4B0000–4BFFFF4C0000–4CFFFF4D0000–4DFFFF4E0000–4EFFFF4F0000–4FFFFF500000–50FFFF510000–51FFFF520000–52FFFF530000–53FFFF0000–FFFF550000–55FFFF560000–56FFFF570000–57FFFF580000–58FFFF590000–59FFFF5A0000–5AFFFF5B0000–5BFFFF5C0000–5CFFFF5D0000–5DFFFF5E0000–5EFFFF5F0000–5FFFFF600000–60FFFF

January 10, 2002Am29LV065D13

Table 2.

SectorSA97SA98SA99SA100SA101SA102SA103SA104SA105SA106SA107SA108SA109SA110SA111SA112SA113SA114SA115SA116SA117SA118SA119SA120SA121SA122SA123SA124SA125SA126SA127

A221111111111111111111111111111111

A211111111111111111111111111111111

A200000000000000001111111111111111

Sector Address Table (Continued)

A190000000111111110000000011111111

A180001111000011110000111100001111

A170110011001100110011001100110011

A161010101010101010101010101010101

8-bit Address Range(in hexadecimal)610000–61FFFF620000–62FFFF630000–63FFFF0000–FFFF650000–65FFFF660000–66FFFF670000–67FFFF680000–68FFFF690000–69FFFF6A0000–6AFFFF6B0000–6BFFFF6C0000–6CFFFF6D0000–6DFFFF6E0000–6EFFFF6F0000–6FFFFF700000–70FFFF710000–71FFFF720000–72FFFF730000–73FFFF740000–74FFFF750000–75FFFF760000–76FFFF770000–77FFFF780000–78FFFF790000–79FFFF7A0000–7AFFFF7B0000–7BFFFF7C0000–7CFFFF7D0000–7DFFFF7E0000–7EFFFF7F0000–7FFFFF

Note: All sectors are Kbytes in size.

14Am29LV065DJanuary 10, 2002

Autoselect Mode

The autoselect mode provides manufacturer and de-vice identification, and sector protection verification,through identifier codes output on DQ7–DQ0. Thismode is primarily intended for programming equip-ment to automatically match a device to be pro-grammed with its corresponding programmingalgorithm. However, the autoselect codes can also beaccessed in-system through the command register.When using programming equipment, the autoselectmode requires VID (8.5 V to 12.5 V) on address pin A9.Address pins A6, A1, and A0 must be as shown in

Table 3. In addition, when verifying sector protection,the sector address must appear on the appropriatehighest order address bits (see Table 2). Table 3shows the remaining address bits that are don’t care.When all necessary bits have been set as required,the programming equipment may then read the corre-sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the hostsystem can issue the autoselect command via thecommand register, as shown in Table 10. This methoddoes not require VID. Refer to the Autoselect Com-mand Sequence section for more information.

Table 3.Am29LV065D Autoselect Codes, (HighVoltageMethod)

A22to A16XXSAX

A15toA10XXXX

A8toA7XXXX

A5toA2XXXX

Description

Manufacturer ID: AMDDevice ID: Am29LV065DSector Protection Verification

SecSi Sector Indicator Bit (DQ7)

CE#OE#WE#LLLL

LLLL

HHHH

A9VIDVIDVIDVID

A6LLLL

A1LLHH

A0LHLH

DQ7 to DQ0

01h93h

80h (protected),00h (unprotected)90h (factory locked),10h (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

January 10, 2002Am29LV065D15

Sector Group Protection and Unprotection

The hardware sector group protection feature disablesboth program and erase operations in any sectorgroup. In this device, a sector group consists of fouradjacent sectors that are protected or unprotected atthe same time (see Table 4). The hardware sectorgroup unprotection feature re-enables both programand erase operations in previously protected sectorgroups. Sector group protection/unprotection can beimplemented via two methods.

Sector protection and unprotection requires VID on theRESET# pin only, and can be implemented eitherin-system or via programming equipment. Figure 2shows the algorithms and Figure 22 shows the timingdiagram. This method uses standard microprocessorbus cycle timing. For sector group unprotect, all unpro-tected sector groups must first be protected prior tothe first sector group unprotect write cycle.

The device is shipped with all sector groups unpro-tected. AMD offers the option of programming andprotecting sector groups at its factory prior to shippingthe device through AMD’s ExpressFlash™ Service.Contact an AMD representative for details.

It is possible to determine whether a sector group isprotected or unprotected. See the Autoselect Modesection for details.

Table 4.

Sector Group Protection/Unprotection

AddressTable

A22–A180000000001000100001100100001010011000111010000100101010010110110001101011100111110000100011001010011101001010110110101111100011001110101101111100111011111011111

Sector GroupSA0–SA3SA4–SA7SA8–SA11SA12–SA15SA16–SA19SA20–SA23SA24–SA27SA28–SA31SA32–SA35SA36–SA39SA40–SA43SA44–SA47SA48–SA51SA52–SA55SA56–SA59SA60–SA63SA–SA67SA68–SA71SA72–SA75SA76–SA79SA80–SA83SA84–SA87SA88–SA91SA92–SA95SA96–SA99SA100–SA103SA104–SA107SA108–SA111SA112–SA115SA116–SA119SA120–SA123SA124–SA127

Note: All sector groups are 256 Kbytes in size.

16Am29LV065DJanuary 10, 2002

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four adjacentsectors that are protected or unprotected at the same time(see Table 4)).

START

This feature allows temporary unprotection of previ-ously protected sector groups to change data in-sys-tem. The Sector Group Unprotect mode is activated bysetting the RESET# pin to VID (8.5 V – 12.5 V). Duringthis mode, formerly protected sector groups can beprogrammed or erased by selecting the sector groupaddresses. Once VID is removed from the RESET#pin, all the previously protected sector groups areprotectedagain. Figure 1 shows the algorithm, andFigure 21 shows the timing diagrams, for this feature.

RESET# = VID

(Note 1)Perform Erase orProgram Operations

RESET# = VIH

Temporary SectorGroup Unprotect Completed (Note 2)

Notes:

1.All protected sector groups unprotected.

2.All previously protected sector groups are protected

once again.

Figure 1.Temporary Sector Group

UnprotectOperation

January 10, 2002Am29LV065D17

STARTPLSCNT = 1RESET# = VIDWait 1 µsProtect all sectorgroups: The indicatedportion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 µsTemporary Sector Group Unprotect ModeNoFirst Write Cycle = 60h?YesSet up sectorgroup addressNoFirst Write Cycle = 60h?NoTemporary SectorGroup Unprotect ModeYesAll sectorgroupsprotected?YesSet up first sector group addressSector Group Unprotect:Write 60h to sectorgroup address withA6 = 1, A1 = 1, A0 = 0ResetPLSCNT = 1Wait 15 msSector Group Protect:Write 60h to sectorgroup address withA6 = 0, A1 = 1, A0 = 0Wait 150 µsVerify Sector Group Protect: Write 40h to sector group address twith A6 = 0, A1 = 1, A0 = 0IncrementPLSCNTRead from sector group addresswith A6 = 0, A1 = 1, A0 = 0NoNoPLSCNT= 25?Data = 01h?IncrementPLSCNTVerify Sector GroupUnprotect: Write 40h to sector groupaddress with A6 = 1, A1 = 1, A0 = 0YesYesRead from sector group address with A6 = 1, A1 = 1, A0 = 0NoYesPLSCNT= 1000?YesSet upnext sector groupaddressData = 00h?Device failedProtectanothersector group?NoRemove VID from RESET#NoYesDevice failedWrite reset commandLast sectorgroupverified?YesNoSector Group ProtectAlgorithmSector Group Protect completeSector Group UnprotectAlgorithmRemove VID from RESET#Write reset commandSector Group Unprotect completeFigure 2.In-System Sector Group Protect/UnprotectAlgorithms

18Am29LV065DJanuary 10, 2002

SecSi (Secured Silicon) Sector Flash MemoryRegion

The SecSi (Secured Silicon) Sector feature provides aFlash memory region that enables permanent partidentification through an Electronic Serial Number(ESN). The SecSi Sector is 256 bytes in length, anduses a SecSi Sector Indicator Bit (DQ7) to indicatewhether or not the SecSi Sector is locked whenshipped from the factory. This bit is permanently set atthe factory and cannot be changed, which preventscloning of a factory locked part. This ensures the secu-rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector eitherfactory locked or customer lockable. The fac-tory-locked version is always protected when shippedfrom the factory, and has the SecSi (Secured Silicon)Sector Indicator Bit permanently set to a “1.” The cus-tomer-lockable version is shipped with the SecSi Sec-tor unprotected, allowing customers to utilize thatsector in any manner they choose. The customer-lock-able version also has the SecSi Sector Indicator Bitpermanently set to a “0.” Thus, the SecSi Sector Indi-cator Bit prevents customer-lockable devices frombeing used to replace devices that are factory locked.The SecSi sector address space in this device is allo-cated as follows:

Table 5.

SecSi Sector Address Range000000h–00000Fh000010h–00007Fh,000400h–00047Fh

SecSi Sector permanently locked. Contact an AMDrepresentative for details on using AMD’s Express-Flash service.

Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory

As an alternative to the factory-locked version, the de-vice may be ordered such that the customer may pro-gram and protect the 256-byte SecSi sector. TheSecSi Sector is one-time programmable, may not beerased, and can be locked only once. Note that the ac-celerated programming (ACC) and unlock bypassfunctions are not available when programming theSecSi Sector.

The SecSi Sector area can be protected using one ofthe following procedures:

sWrite the three-cycle Enter SecSi Sector Regioncommand sequence, and then follow the in-systemsector protect algorithm as shown in Figure 2, ex-cept that RESET# may be at either VIH or VID. Thisallows in-system protection of the SecSi Sectorwithout raising any device pin to a high voltage.Note that this method is only applicable to the SecSiSector.sWrite the three-cycle Enter SecSi Sector Regioncommand sequence, and then use the method ofsector protection described in the “Sector GroupProtection and Unprotection” section.The SecSi Sector is one-time programmable. Oncethe SecSi Sector is programmed, locked and verified,the system must write the Exit SecSi Sector Regioncommand sequence to return to reading and writingthe remainder of the array.

The SecSi Sector protection must be used with cau-tion since, once protected, there is no procedure avail-able for unprotecting the SecSi Sector area and noneof the bits in the SecSi Sector memory space can bemodified in any way.

SecSi Sector Contents

Customer Lockable

Standard ExpressFlashFactory LockedFactory Locked

ESNUnavailable

ESN or determined by customerDetermined by customer

Determined by customer

The system accesses the SecSi Sector through acommand sequence (see “Enter SecSi Sector/ExitSecSi Sector CommandSequence”). After the systemhas written the Enter SecSi Sector command se-quence, it may read the SecSi Sector by using the ad-dresses normally occupied by the first sector (SA0).This mode of operation continues until the system is-sues the Exit SecSi Sector command sequence, oruntil power is removed from the device. On power-up,or following a hardware reset, the device reverts tosending commands to sector SA0.

Factory Locked: SecSi Sector Programmed and Protected At the Factory

In devices with an ESN, the SecSi Sector is protectedwhen the device is shipped from the factory. The SecSiSector cannot be modified in any way. A factory lockeddevice has an 16-byte random ESN at addresses000000h–00000Fh.

Customers may opt to have their code programmed byAMD through the AMD ExpressFlash service. The de-vices are then shipped from AMD’s factory with the

Hardware Data Protection

The command sequence requirement of unlock cyclesfor programming or erasing provides data protectionagainst inadvertent writes (refer to Table 10 for com-mand definitions). In addition, the following hardwaredata protection measures prevent accidental erasureor programming, which might otherwise be caused byspurious system level signals during VCC power-upand power-down transitions, or from system noise.Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-cept any write cycles. This protects data during VCCpower-up and power-down. The command registerand all internal program/erase circuits are disabled,and the device resets to the read mode. Subsequent

January 10, 2002Am29LV065D19

writes are ignored until VCC is greater than VLKO. Thesystem must provide the proper signals to the controlpins to prevent unintentional writes when VCC isgreater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,CE# and WE# must be a logical zero while OE# is alogical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up,the device does not accept commands on the risingedge of WE#. The internal state machine is automati-cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-lines device and host system software interrogationhandshake, which allows specific vendor-specifiedsoftware algorithms to be used for entire families ofdevices. Software support can then be device-inde-pendent, JEDEC ID-independent, and forward- andbackward-compatible for the specified flash devicefamilies. Flash vendors can standardize their existinginterfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-tem writes the CFI Query command, 98h, any time thedevice is ready to read array data (addresses are don’tcare). The system can read CFI information at the ad-dresses given in Tables 6–9. To terminate reading CFIdata, the system must write the reset command. The system can also write the CFI query commandwhen the device is in the autoselect mode. The deviceenters the CFI query mode, and the system can readCFI data at the addresses given in Tables 6–9. Thesystem must write the reset command to return the de-vice to the autoselect mode.

For further information, please refer to the CFI Specifi-cation and CFI Publication 100, available via theWorld Wide Web at http://www.amd.com/prod-ucts/nvd/overview/cfi.html. Alternatively, contact anAMD representative for copies of these documents.

Table 6.

Addresses (x8)

10h11h12h13h14h15h16h17h18h19h1Ah

Data51h52h59h02h00h40h00h00h00h00h00h

CFI Query Identification String

Description

Query Unique ASCII string “QRY”

Primary OEM Command SetAddress for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

20Am29LV065DJanuary 10, 2002

Table 7.System Interface String

Addresses (x8)

1Bh1Ch1Dh1Eh1Fh20h21h22h23h24h25h26h

Data27h36h00h00h04h00h0Ah00h05h00h04h00h

VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

VPP Min. voltage (00h = no VPP pin present)VPP Max. voltage (00h = no VPP pin present)Typical timeout per single byte write 2N µs

Typical timeout for Min. size buffer write 2N µs (00h = not supported)Typical timeout per individual block erase 2N ms

Typical timeout for full chip erase 2N ms (00h = not supported)Max. timeout for byte write 2N times typicalMax. timeout for buffer write 2N times typical

Max. timeout per individual block erase 2N times typical

Max. timeout for full chip erase 2N times typical (00h = not supported)

Description

Table 8.

Addresses (x8)

27h28h29h2Ah2Bh2Ch2Dh2Eh2Fh30h31h32h33h34h35h36h37h38h39h3Ah3Bh3Ch

Data17h00h00h00h00h01h7Fh00h00h01h00h00h00h00h00h00h00h00h00h00h00h00h

Device Geometry Definition

Description

Device Size = 2N byte

Flash Device Interface description (refer to CFI publication 100)Max. number of bytes in multi-byte write = 2N (00h = not supported)

Number of Erase Block Regions within deviceErase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

January 10, 2002Am29LV065D21

Table 9.Primary Vendor-Specific Extended Query

Addresses (x8)

40h41h42h43h44h45h

Data50h52h49h31h31h01h

Query-unique ASCII string “PRI”Major version number, ASCIIMinor version number, ASCIIAddress Sensitive Unlock (Bits 1-0)0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2)

46h47h48h49h4Ah4Bh4Ch4Dh

02h04h01h04h00h000h00hB5h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & WriteSector Protect

0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect

00 = Not Supported, 01 = SupportedSector Protect/Unprotect scheme 04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type

00 = Not Supported, 01 = SupportedPage Mode Type00 = Not Supported

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mVACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mVTop/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

Description

4EhC5h

4Fh00h

COMMAND DEFINITIONS

Writing specific address and data commands or se-quences into the command register initiates device op-erations. Table 10 defines the valid register commandsequences. Writing incorrect address and data val-ues or writing them in the improper sequence resetsthe device to reading array data.

All addresses are latched on the falling edge of WE#or CE#, whichever happens later. All data is latched onthe rising edge of WE# or CE#, whichever happensfirst. Refer to the AC Characteristics section for timingdiagrams.

after completing an Embedded Program or EmbeddedErase algorithm.

After the device accepts an Erase Suspend command,the device enters the erase-suspend-read mode, afterwhich the system can read data from anynon-erase-suspended sector. After completing a pro-gramming operation in the Erase Suspend mode, thesystem may once again read array data with the sameexception. See the Erase Suspend/Erase ResumeCommands section for more information.

The system must issue the reset command to returnthe device to the read (or erase-suspend-read) modeif DQ5 goes high during an active program or eraseoperation, or if the device is in the autoselect mode.See the next section, Reset Command, for more infor-mation.

Reading Array Data

The device is automatically set to reading array dataafter device power-up. No commands are required toretrieve data. The device is ready to read array data

22Am29LV065DJanuary 10, 2002

See also “VersatileIOTM (VIO) Control” in the DeviceBus Operations section for more information. TheRead-Only Operations table provides the read param-eters, and Figure 13 shows the timing diagram.

device then enters the autoselect mode. The systemmay read at any address any number of times withoutinitiating another autoselect command sequence.The system must write the reset command to return tothe read mode (or erase-suspend-read mode if the de-vice was previously in Erase Suspend).

Reset Command

Writing the reset command resets the device to theread or erase-suspend-read mode. Address bits aredon’t cares for this command.

The reset command may be written between the se-quence cycles in an erase command sequence beforeerasing begins. This resets the device to the readmode. Once erasure begins, however, the device ig-nores reset commands until the operation is complete.The reset command may be written between thesequence cycles in a program command sequencebefore programming begins. This resets the device tothe read mode. If the program command sequence iswritten while the device is in the Erase Suspend mode,writing the reset command returns the device to theerase-suspend-read mode. Once programming be-gins, however, the device ignores reset commandsuntil the operation is complete.

The reset command may be written between the se-quence cycles in an autoselect command sequence.Once in the autoselect mode, the reset commandmust be written to return to the read mode. If the de-vice entered the autoselect mode while in the EraseSuspend mode, writing the reset command returns thedevice to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,writing the reset command returns the device to theread mode (or erase-suspend-read mode if the devicewas in Erase Suspend).

Enter SecSi Sector/Exit SecSi SectorCommandSequence

The SecSi Sector region provides a secured data areacontaining an 16-byte random Electronic Serial Num-ber (ESN). The system can access the SecSi Sectorregion by issuing the three-cycle Enter SecSi Sectorcommand sequence. The device continues to accessthe SecSi Sector region until the system issues thefour-cycle Exit SecSi Sector command sequence. TheExit SecSi Sector command sequence returns the de-vice to normal operation. Table 10 shows the addressand data requirements for both command sequences.See also “SecSi (Secured Silicon) Sector FlashMemoryRegion” for further information.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-gram command sequence is initiated by writing twounlock write cycles, followed by the program set-upcommand. The program address and data are writtennext, which in turn initiate the Embedded Program al-gorithm. The system is not required to provide furthercontrols or timings. The device automatically providesinternally generated program pulses and verifies theprogrammed cell margin. Table 10 shows the addressand data requirements for the byte program commandsequence.

When the Embedded Program algorithm is complete,the device then returns to the read mode and ad-dresses are no longer latched. The system can deter-mine the status of the program operation by usingDQ7, DQ6, or RY/BY#. Refer to the Write OperationStatus section for information on these status bits.Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that ahardware reset immediately terminates the programoperation. The program command sequence shouldbe reinitiated once the device has returned to the readmode, to ensure data integrity.

Programming is allowed in any sequence and acrosssector boundaries. A bit cannot be programmedfrom “0” back to a “1.” Attempting to do so maycause the device to set DQ5 = 1, or cause the DQ7and DQ6 status bits to indicate the operation was suc-cessful. However, a succeeding read will show that thedata is still “0.” Only erase operations can convert a“0” to a “1.”

Autoselect Command Sequence

The autoselect command sequence allows the hostsystem to read several identifier codes at specific ad-dresses:

Identifier CodeManufacturer IDDevice ID

SecSi Sector Factory ProtectSector Group Protect Verify

Address00h01h03h(SA)02h

Table 10 shows the address and data requirements.The command sequence is an alternative to the highvoltage method shown in Table 3. The autoselect com-mand sequence may be written to an address that iseither in the read or erase-suspend-read mode. Theautoselect command may not be written while the de-vice is actively programming or erasing.

The autoselect command sequence is initiated by firstwriting two unlock cycles. This is followed by a thirdwrite cycle that contains the autoselect command. TheJanuary 10, 2002

Am29LV065D23

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-gram bytes to the device faster than using the stan-dard program command sequence. The unlockbypass command sequence is initiated by first writingtwo unlock cycles. This is followed by a third writecycle containing the unlock bypass command, 20h.The device then enters the unlock bypass mode. Atwo-cycle unlock bypass program command sequenceis all that is required to program in this mode. The firstcycle in this sequence contains the unlock bypass pro-gram command, A0h; the second cycle contains theprogram address and data. Additional data is pro-grammed in the same manner. This mode dispenseswith the initial two unlock cycles required in the stan-dard program command sequence, resulting in fastertotal programming time. Table 10 shows the require-ments for the command sequence.

During the unlock bypass mode, only the Unlock By-pass Program and Unlock Bypass Reset commandsare valid. To exit the unlock bypass mode, the systemmust issue the two-cycle unlock bypass reset com-mand sequence. The first cycle must contain the data90h. The second cycle must contain the data 00h. Thedevice then returns to the read mode.

The device offers accelerated program operationsthrough the ACC pin. When the system asserts VHH onthe ACC pin, the device automatically enters the Un-lock Bypass mode. The system may then write thetwo-cycle Unlock Bypass program command se-quence. The device uses the higher voltage on theACC pin to accelerate the operation. Note that theACC pin must not be at VHH for operations other thanaccelerated programming, or device damage may re-sult.

Figure 3 illustrates the algorithm for the program oper-ation. Refer to the Erase and Program Operationstable in the AC Characteristics section for parameters,and Figure 15 for timing diagrams.

STARTWrite ProgramCommand SequenceEmbedded Programalgorithm in progressData Poll from SystemVerify Data?NoYesNoIncrement AddressLast Address?YesProgramming CompletedNote: See Table 10 for program command sequence.

Figure 3.Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erasecommand sequence is initiated by writing two unlockcycles, followed by a set-up command. Two additionalunlock write cycles are then followed by the chip erasecommand, which in turn invokes the Embedded Erasealgorithm. The device does not require the system topreprogram prior to erase. The Embedded Erase algo-rithm automatically preprograms and verifies the entirememory for an all zero data pattern prior to electricalerase. The system is not required to provide any con-trols or timings during these operations. Table 10shows the address and data requirements for the chiperase command sequence.

24Am29LV065DJanuary 10, 2002

When the Embedded Erase algorithm is complete, thedevice returns to the read mode and addresses are nolonger latched. The system can determine the statusof the erase operation by using DQ7, DQ6, DQ2, orRY/BY#. Refer to the Write Operation Status sectionfor information on these status bits.

Any commands written during the chip erase operationare ignored. However, note that a hardware reset im-mediately terminates the erase operation. If that oc-curs, the chip erase command sequence should bereinitiated once the device has returned to readingarray data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-tion. Refer to the Erase and Program Operations ta-bles in the AC Characteristics section for parameters,and Figure 17 section for timing diagrams.

When the Embedded Erase algorithm is complete, thedevice returns to reading array data and addressesare no longer latched. Note that while the EmbeddedErase operation is in progress, the system can readdata from the non-erasing sector. The system can de-termine the status of the erase operation by readingDQ7, DQ6, DQ2, or RY/BY# in the erasing sector.Refer to the Write Operation Status section for infor-mation on these status bits.

Once the sector erase operation has begun, only theErase Suspend command is valid. All other com-mands are ignored. However, note that a hardwarereset immediately terminates the erase operation. Ifthat occurs, the sector erase command sequenceshould be reinitiated once the device has returned toreading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-tion. Refer to the Erase and Program Operations ta-bles in the AC Characteristics section for parameters,and Figure 17 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sectorerase command sequence is initiated by writing twounlock cycles, followed by a set-up command. Two ad-ditional unlock cycles are written, and are then fol-lowed by the address of the sector to be erased, andthe sector erase command. Table 10 shows the ad-dress and data requirements for the sector erase com-mand sequence.

The device does not require the system to preprogramprior to erase. The Embedded Erase algorithm auto-matically programs and verifies the entire memory foran all zero data pattern prior to electrical erase. Thesystem is not required to provide any controls or tim-ings during these operations.

After the command sequence is written, a sector erasetime-out of 50 µs occurs. During the time-out period,additional sector addresses and sector erase com-mands may be written. Loading the sector erase buffermay be done in any sequence, and the number of sec-tors may be from one sector to all sectors. The timebetween these additional cycles must be less than 50µs, otherwise erasure may begin. Any sector eraseaddress and command following the exceededtime-out may or may not be accepted. It is recom-mended that processor interrupts be disabled duringthis time to ensure all commands are accepted. Theinterrupts can be re-enabled after the last SectorErase command is written. Any command other thanSector Erase or Erase Suspend during thetime-out period resets the device to the readmode. The system must rewrite the command se-quence and any additional addresses and commands.The system can monitor DQ3 to determine if the sec-tor erase timer has timed out (See the section on DQ3:Sector Erase Timer.). The time-out begins from the ris-ing edge of the final WE# pulse in the commandsequence.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the sys-tem to interrupt a sector erase operation and then readdata from, or program data to, any sector not selectedfor erasure. This command is valid only during thesector erase operation, including the 50 µs time-outperiod during the sector erase command sequence.The Erase Suspend command is ignored if written dur-ing the chip erase operation or Embedded Programalgorithm.

When the Erase Suspend command is written duringthe sector erase operation, the device requires a max-imum of 20 µs to suspend the erase operation. How-ever, when the Erase Suspend command is writtenduring the sector erase time-out, the device immedi-ately terminates the time-out period and suspends theerase operation.

After the erase operation has been suspended, thedevice enters the erase-suspend-read mode. The sys-tem can read data from or program data to any sectornot selected for erasure. (The device “erase sus-pends” all sectors selected for erasure.) Reading atany address within erase-suspended sectors pro-duces status information on DQ7–DQ0. The systemcan use DQ7, or DQ6 and DQ2 together, to determineif a sector is actively erasing or is erase-suspended.Refer to the Write Operation Status section for infor-mation on these status bits.

After an erase-suspended program operation is com-plete, the device returns to the erase-suspend-readmode. The system can determine the status of theprogram operation using the DQ7 or DQ6 status bits,just as in the standard byte program operation.

January 10, 2002Am29LV065D25

Referto the Write Operation Status section for moreinformation.

In the erase-suspend-read mode, the system can alsoissue the autoselect command sequence. Refer to theAutoselect Mode and Autoselect Command Sequencesections for details.

To resume the sector erase operation, the systemmust write the Erase Resume command. The addressof the erase-suspended sector is required when writ-ing this command. Further writes of the Resume com-mand are ignored. Another Erase Suspend commandcan be written after the chip has resumed erasing.

STARTWrite Erase Command Sequence(Notes 1, 2)Data Poll to Erasing Bank from SystemNoEmbedded Erasealgorithmin progressData = FFh?YesErasure CompletedNotes:

1.See Table 10 for erase command sequence.2.See the section on DQ3 for information on the sector

erase timer.

Figure 4.Erase Operation

26Am29LV065DJanuary 10, 2002

Command Definitions

Table 10.Am29LV065D Command Definitions

CommandSequence(Note 1)

Read (Note 5)Reset (Note 6)Autoselect (Note 7)Manufacturer IDDevice ID

SecSi Sector Factory Protect (Note 8)

Sector Group Protect Verify (Note 9)

CyclesBus Cycles (Notes 2–4)

FirstAddrRAXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXBABAXX

DataRDF0AAAAAAAAAAAAAAAAA090AAAAB03098

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A22–A16 uniquely select any sector.

XXXXXXXXXXXXXXXXXXXXXXXXPAXXXXXXXXX

5555555555555555PD005555

XXXXXX

8080

XXXXXX

AAAA

XXXXXX

5555

XXXSA

1030

XXXXXXXXXXXXXXXXXXXXXXXX

9090909080A020

XXXPA

00PD

X00X01X03(SA)X02

019380/0000/01

Second Third Addr

Data

Addr

Data

Fourth Fifth Sixth Data

Addr

Data

Addr

Data

Addr

114444344

Enter SecSi Sector RegionExit SecSi Sector RegionProgramUnlock Bypass

3

Unlock Bypass Program (Note 10)2Unlock Bypass Reset (Note 11)2

Chip EraseSector Erase

Erase Suspend (Note 12)Erase Resume (Note 13)CFI Query (Note 14)

66111

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.

Notes:

1.See Table 1 for description of bus operations.2.3.4.5.6.

All values are in hexadecimal.

Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

Unless otherwise noted, address bits A22–A12 are don’t cares.No unlock or command cycles required when device is in read mode.

The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information).

The fourth cycle of the autoselect command sequence is a read cycle. See the Autoselect Command Sequence section for more information.

The data is 80h for factory locked and 00h for not factory locked.

9.

The data is 00h for an unprotected sector group and 01h for a protected sector group.

10.The Unlock Bypass command is required prior to the Unlock

Bypass Program command.11.The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.12.The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.13.The Erase Resume command is valid only during the Erase

Suspend mode.

14.Command is valid when device is ready to read array data or when

device is in autoselect mode.

7.

8.

January 10, 2002Am29LV065D27

WRITE OPERATION STATUS

The device provides several bits to determine the status ofa program or erase operation: DQ2, DQ3, DQ5, DQ6, andDQ7. Table 11 and the following subsections describe thefunction of these bits. DQ7 and DQ6 each offer a methodfor determining whether a program or erase operation iscomplete or in progress. The device also provides a hard-ware-based output signal, RY/BY#, to determine whetheran Embedded Program or Erase operation is in progress orhas been completed.

valid data, the data outputs on DQ0–DQ6 may be stillinvalid. Valid data on DQ0–DQ7 will appear on suc-cessive read cycles.

Table 11 shows the outputs for Data# Polling on DQ7.Figure 5 shows the Data# Polling algorithm. Figure 18in the AC Characteristics section shows the Data#Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host systemwhether an Embedded Program or Erase algorithm is inprogress or completed, or whether the device is in EraseSuspend. Data# Polling is valid after the rising edge of thefinal WE# pulse in the command sequence.

During the Embedded Program algorithm, the device out-puts on DQ7 the complement of the datum programmed toDQ7. This DQ7 status also applies to programming duringErase Suspend. When the Embedded Program algorithm iscomplete, the device outputs the datum programmed toDQ7. The system must provide the program address toread valid status information on DQ7. If a program addressfalls within a protected sector, Data# Polling on DQ7 is ac-tive for approximately 1 µs, then the device returns to theread mode.

During the Embedded Erase algorithm, Data# Pollingproduces a “0” on DQ7. When the Embedded Erasealgorithm is complete, or if the device enters the EraseSuspend mode, Data# Polling produces a “1” on DQ7.The system must provide an address within any of thesectors selected for erasure to read valid status infor-mation on DQ7.

After an erase command sequence is written, if allsectors selected for erasing are protected, Data# Poll-ing on DQ7 is active for approximately 100 µs, thenthe device returns to the read mode. If not all selectedsectors are protected, the Embedded Erase algorithmerases the unprotected sectors, and ignores the se-lected sectors that are protected. However, if the sys-tem reads DQ7 at an address within a protectedsector, the status may not be valid.

Just prior to the completion of an Embedded Programor Erase operation, DQ7 may change asynchronouslywith DQ0–DQ6 while Output Enable (OE#) is assertedlow. That is, the device may change from providingstatus information to valid data on DQ7. Depending onwhen the system samples the DQ7 output, it may readthe status or valid data. Even if the device has com-pleted the program or erase operation and DQ7 has

STARTRead DQ7–DQ0Addr = VADQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSNotes:

1.VA = Valid address for programming. During a sector

erase operation, a valid address is any sector addresswithin the sector being erased. During chip erase, avalid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5.Data# Polling Algorithm

28Am29LV065DJanuary 10, 2002

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pinwhich indicates whether an Embedded Algorithm is inprogress or complete. The RY/BY# status is valid afterthe rising edge of the final WE# pulse in the commandsequence. Since RY/BY# is an open-drain output, sev-eral RY/BY# pins can be tied together in parallel with apull-up resistor to VCC.

If the output is low (Busy), the device is actively eras-ing or programming. (This includes programming inthe Erase Suspend mode.) If the output is high(Ready), the device is in the read mode, the standbymode, or the device is in the erase-suspend-readmode.

Table 11 shows the outputs for RY/BY#.

Table 11 shows the outputs for Toggle Bit I on DQ6.Figure 6 shows the toggle bit algorithm. Figure 19 inthe “AC Characteristics” section shows the toggle bittiming diagrams. Figure 20 shows the differences be-tween DQ2 and DQ6 in graphical form. See also thesubsection on DQ2: Toggle Bit II.

STARTRead DQ7–DQ0DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an EmbeddedProgram or Erase algorithm is in progress or com-plete, or whether the device has entered the EraseSuspend mode. Toggle Bit I may be read at any ad-dress, and is valid after the rising edge of the finalWE# pulse in the command sequence (prior to theprogram or erase operation), and during the sectorerase time-out.

During an Embedded Program or Erase algorithm op-eration, successive read cycles to any address causeDQ6 to toggle. The system may use either OE# orCE# to control the read cycles. When the operation iscomplete, DQ6 stops toggling.

After an erase command sequence is written, if all sectorsselected for erasing are protected, DQ6 toggles for approxi-mately 100 µs, then returns to reading array data. If not allselected sectors are protected, the Embedded Erase algo-rithm erases the unprotected sectors, and ignores the se-lected sectors that are protected.

The system can use DQ6 and DQ2 together to determinewhether a sector is actively erasing or is erase-suspended.When the device is actively erasing (that is, the EmbeddedErase algorithm is in progress), DQ6 toggles. When the de-vice enters the Erase Suspend mode, DQ6 stops toggling.However, the system must also use DQ2 to determinewhich sectors are erasing or erase-suspended. Alterna-tively, the system can use DQ7 (see the subsection onDQ7: Data# Polling).

If a program address falls within a protected sector,DQ6 toggles for approximately 1 µs after the programcommand sequence is written, then returns to readingarray data.

DQ6 also toggles during the erase-suspend-programmode, and stops toggling once the Embedded Pro-gram algorithm is complete.

NoRead DQ7–DQ0Toggle Bit = Toggle?YesNoDQ5 = 1?YesRead DQ7–DQ0TwiceToggle Bit = Toggle?YesProgram/EraseOperation Not Complete, Write Reset CommandNoProgram/EraseOperation CompleteNote: The system should recheck the toggle bit even ifDQ5 = “1” because the toggle bit may stop toggling as DQ5changes to “1.” See the subsections on DQ6 and DQ2 formore information.

Figure 6.Toggle Bit Algorithm

January 10, 2002Am29LV065D29

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing(that is, the Embedded Erase algorithm is in progress),or whether that sector is erase-suspended. Toggle BitII is valid after the rising edge of the final WE# pulse inthe command sequence.

DQ2 toggles when the system reads at addresseswithin those sectors that have been selected for era-sure. (The system may use either OE# or CE# to con-trol the read cycles.) But DQ2 cannot distinguishwhether the sector is actively erasing or is erase-sus-pended. DQ6, by comparison, indicates whether thedevice is actively erasing, or is in Erase Suspend, butcannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector andmode information. Refer to Table 11 to compare out-puts for DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchartform, and the section “DQ2: Toggle Bit II” explains thealgorithm. See also the DQ6: Toggle Bit I subsection.Figure 19 shows the toggle bit timing diagram. Figure20 shows the differences between DQ2 and DQ6 ingraphical form.

the toggle bit and DQ5 through successive read cy-cles, determining the status as described in the previ-ous paragraph. Alternatively, it may choose to performother system tasks. In this case, the system must startat the beginning of the algorithm when it returns to de-termine the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time hasexceeded a specified internal pulse count limit. Under theseconditions DQ5 produces a “1,” indicating that the programor erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system triesto program a “1” to a location that was previously pro-grammed to “0.” Only an erase operation canchange a “0” back to a “1.” Under this condition, thedevice halts the operation, and when the timing limithas been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must writethe reset command to return to the read mode (or tothe erase-suspend-read mode if the device was previ-ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, thesystem may read DQ3 to determine whether or noterasure has begun. (The sector erase timer does notapply to the chip erase command.) If additionalsectors are selected for erasure, the entire time-outalso applies after each additional sector erase com-mand. When the time-out period is complete, DQ3switches from a “0” to a “1.” If the time between addi-tional sector erase commands from the system can beassumed to be less than 50 µs, the system need notmonitor DQ3. See also the Sector Erase CommandSequence section.

After the sector erase command is written, the systemshould read the status of DQ7 (Data# Polling) or DQ6(Toggle Bit I) to ensure that the device has acceptedthe command sequence, and then read DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all fur-ther commands (except Erase Suspend) are ignoreduntil the erase operation is complete. If DQ3 is “0,” thedevice will accept additional sector erase commands.To ensure the command has been accepted, the sys-tem software should check the status of DQ3 prior toand following each subsequent sector erase com-mand. If DQ3 is high on the second status check, thelast command might not have been accepted.Table 11 shows the status of DQ3 relative to the otherstatus bits.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-ever the system initially begins reading toggle bit sta-tus, it must read DQ7–DQ0 at least twice in a row todetermine whether a toggle bit is toggling. Typically,the system would note and store the value of the tog-gle bit after the first read. After the second read, thesystem would compare the new value of the toggle bitwith the first. If the toggle bit is not toggling, the devicehas completed the program or erase operation. Thesystem can read array data on DQ7–DQ0 on the fol-lowing read cycle.

However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, the sys-tem also should note whether the value of DQ5 is high(see the section on DQ5). If it is, the system shouldthen determine again whether the toggle bit is tog-gling, since the toggle bit may have stopped togglingjust as DQ5 went high. If the toggle bit is no longertoggling, the device has successfully completed theprogram or erase operation. If it is still toggling, the de-vice did not completed the operation successfully, andthe system must write the reset command to return toreading array data.

The remaining scenario is that the system initially de-termines that the toggle bit is toggling and DQ5 hasnot gone high. The system may continue to monitor

30Am29LV065DJanuary 10, 2002

Table 11.

Status

Standard Embedded Program AlgorithmModeEmbedded Erase Algorithm

Erase

Erase-Suspend-Suspended SectorErase

ReadNon-Erase Suspend

Suspended SectorMode

Erase-Suspend-Program

Write Operation Status

DQ7(Note 2)DQ7#0

1DataDQ7#

DQ6ToggleToggleNo toggleDataToggle

DQ5(Note 1)

00

0Data0

DQ3N/A1N/ADataN/A

DQ2(Note 2)No toggleToggleToggleDataN/A

RY/BY#

00

110

Notes:

1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

January 10, 2002Am29LV065D31

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°CAmbient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°CVoltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 VVIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 VA9, OE#, ACC, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 VAll other pins (Note 1). . . . . . –0.5 V to VCC +0.5 VOutput Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1.Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins mayovershoot VSS to –2.0 V for periods of up to 20 ns.Maximum DC voltage on input or I/O pins is VCC +0.5 V.See Figure 7. During voltage transitions, input or I/O pinsmay overshoot to VCC +2.0 V for periods up to 20 ns. SeeFigure 8.2.Minimum DC input voltage on pins A9, OE#, ACC, and

RESET# is –0.5 V. During voltage transitions, A9, OE#,ACC, and RESET# may overshoot VSS to –2.0 V forperiods of up to 20 ns. See Figure 7. Maximum DC inputvoltage on pin A9, OE#, ACC, and RESET# is +12.5 Vwhich may overshoot to +14.0 V for periods up to 20 ns.3.No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greaterthan one second.Stresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device. Thisis a stress rating only; functional operation of the device atthese or any other conditions above those indicated in theoperational sections of this data sheet is not implied.Exposure of the device to absolute maximum ratingconditions for extended periods may affect device reliability.

+0.8 V–0.5 V–2.0 V20 ns20 ns20 nsFigure 7. Maximum Negative

OvershootWaveform

20 nsVCC+2.0 VVCC+0.5 V2.0 V

20 ns20 nsFigure 8. Maximum Positive

OvershootWaveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°CExtended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°CSupply Voltages

VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0–3.6 VVIO . . . . . . . . . . . . . . . . .either 1.8–2.9 V or 3.0–5.0 V

(see Ordering Information section)

Operating ranges define those limits between which thefunctionality of the device is guaranteed.

32Am29LV065DJanuary 10, 2002

DC CHARACTERISTICSCMOS Compatible

Parameter Symbol

ILIILITILOICC1ICC2ICC3ICC4ICC5IACCVILVIHVHHVIDVOLVOH1VOH2VLKO

Parameter DescriptionInput Load Current

A9, ACC Input Load CurrentOutput Leakage CurrentVCC Active Read Current (Notes 1, 2)

Test Conditions

VIN = VSS to VCC, VCC = VCC max

VCC = VCC max; A9 = 12.5 VVOUT = VSS to VCC, VCC = VCC max

CE# = VIL, OE# = VIH

5 MHz1 MHz

92260.20.20.2515

–0.50.7 x VCC

VCC = 3.0 V ± 10%VCC = 3.0 V ± 10%

11.58.5Min

Typ

Max±1.035±1.016 43055510300.8VCC + 0.312.512.5

UnitµAµAµAmAmAµAµAµAmAmAVVVVVVV

2.5

V

VCC Active Write Current (Notes 2, 3)CE# = VIL, OE# = VIHVCC Standby Current (Note 2)VCC Reset Current (Note 2)Automatic Sleep Mode (Notes 2, 4)ACC Accelerated Program CurrentInput Low Voltage (Note 5)Input High Voltage (Note 5)Voltage for ACC Program Acceleration

Voltage for Autoselect and Temporary Sector UnprotectOutput Low VoltageOutput High Voltage

Low VCC Lock-Out Voltage (Note 6)

CE#, RESET# = VCC ± 0.3 VRESET# = VSS ± 0.3 V

VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 VCE# = VIL, OE# = VIH

ACC pinVCC pin

IOL = 4.0 mA, VCC = VCC min 0.45VIOIOH = –2.0 mA, VCC = VCC min 0.8 IOH = –100 µA, VCC = VCC min

VIO–0.42.3

Notes:

1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.

2.Maximum ICC specifications are tested with VCC = VCCmax.

3.ICC active while Embedded Erase or Embedded Program is in progress.

4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is

200 nA.

5.If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH

for these connections is VIO + 0.3 V.6.Not 100% tested.

January 10, 2002Am29LV065D33

DC CHARACTERISTICSZero-Power Flash

25Supply Current in mA20151050

0

500

1000

1500

2000Time in ns

2500

3000

3500

4000

Note: Addresses are switching at 1 MHz

Figure 9.

ICC1 Current vs. Time (Showing Active and AutomaticSleepCurrents)

12

3.6 V

10

8Supply Current in mA3.0 V

6

4

2

01

Note: T = 25 °C

2

3

Frequency in MHz

Figure 10.

Typical ICC1 vs. Frequency

45

34Am29LV065DJanuary 10, 2002

TEST CONDITIONS

Table 12.

3.3 V

Test Condition

DeviceUnderTest

CL

6.2 kΩ

2.7 kΩ

Output Load

Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall TimesInput Pulse Levels

Input timing measurement reference levels (See Note)

Note: Diodes are IN30 or equivalent

Output timing measurement reference levels

30

50.0–3.0

Test Specifications

90R, 101R

120R,121R1 TTL gate

100

pFnsVUnit

1.5 V0.5 VIO

V

Figure 11. Test Setup

Note: If VIO < VCC, the reference level is 0.5 VIO.

3.0 V0.0 VInput1.5 VMeasurement Level0.5 VIO VOutputNote: If VIO < VCC, the input measurement reference level is 0.5 VIO.

Figure 12.Input Waveforms and MeasurementLevels

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

Steady

Changing from H to LChanging from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

OUTPUTS

January 10, 2002Am29LV065D35

AC CHARACTERISTICSRead-Only Operations

ParameterJEDECtAVAVtAVQVtELQVtGLQVtEHQZtGHQZtAXQX

Std.tRCtACCtCEtOEtDFtDFtOH

Description

Read Cycle Time (Note 2)Address to Output DelayChip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 2) Output Enable to Output High Z (Note 2)

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs FirstRead

Output Enable

Hold Time (Note 2)Toggle and

Data# Polling

CE#, OE# = VIL

OE# = VILTest Setup(Note 1)

MinMaxMaxMaxMaxMaxMinMinMin

90R909090353030

Speed Options

101R1001001003530300010

120R,121R120120120503030

Unitnsnsnsnsnsnsnsnsns

tOEH

Notes:

1.All test setups assume VIO = VCC.

2.Not 100% tested.

3.See Figure 11 and Table 12 for test specifications.

tRCAddressesCE#Addresses StabletACCtRHtRHOE#tOEHWE#HIGH ZtCEtOHOutput ValidHIGH ZtOEtDFOutputsRESET#RY/BY#0 VFigure 13.Read Operation Timings

36Am29LV065DJanuary 10, 2002

AC CHARACTERISTICSHardware Reset (RESET#)

ParameterJEDEC

StdtReadytReadytRPtRHtRPDtRB

Description

RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note)RESET# Pulse Width

Reset High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time

MaxMaxMinMinMinMin

All Speed Options

2050050050200

Unitµsnsnsnsµsns

Note: Not 100% tested.

RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#RESET#

tRPFigure 14.Reset Timings

January 10, 2002Am29LV065D37

AC CHARACTERISTICSErase and Program Operations

ParameterJEDECtAVAVtAVWL

Std.tWCtAStASO

tWLAX

tAHtAHT

tDVWHtWHDX

tDStDHtOEPH

tGHWLtELWLtWHEHtWLWHtWHDLtWHWH1tWHWH1tWHWH2

tGHWLtCStCHtWPtWPHtWHWH1tWHWH1tWHWH2tVHHtVCStRBtBUSY

Notes:

1.Not 100% tested.

2.See the “Erase And Programming Performance” section for more information.

Description

Write Cycle Time (Note 1)Address Setup Time

Address Setup Time to OE# low during toggle bit polling Address Hold Time

Address Hold Time From CE# or OE# high during toggle bit pollingData Setup TimeData Hold Time

Output Enable High during toggle bit pollingRead Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse WidthWrite Pulse Width High

Byte Programming Operation (Note 2)

Accelerated Byte Programming Operation (Note 2)Sector Erase Operation (Note 2)VHH Rise and Fall Time (Note 1)VCC Setup Time (Note 1)

Write Recovery Time from RY/BY#Program/Erase Valid to RY/BY# Delay

MinMinMinMinMinMinMinMinMinMinMinMinMinTypTypTypMinMinMinMax

35

Speed Options90R90

101R10001504502000035300.925050090

505050120R,121R120

Unitnsnsnsnsnsnsnsnsnsnsnsnsnsµsµssecnsµsnsns

38Am29LV065DJanuary 10, 2002

AC CHARACTERISTICS

Program Command Sequence (last two cycles)tWCAddressesXXXhtASPAtAHCE#OE#tWPWE#tCStDSDatatDHPDtBUSYRY/BY#VCCtVCSNote: PA = program address, PD = program data, DOUT is the true data at the program address.

Read Status Data (last two cycles)PAPAtCHtWHWH1tWPHA0hStatusDOUTtRBFigure 15.Program Operation Timings

VHHACCVIL or VIHtVHHtVHHVIL or VIHFigure 16.Accelerated Program Timing Diagram

January 10, 2002Am29LV065D39

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)tWCAddressesXXXhtASSAXXXh for chip eraseRead Status DataVAtAHVACE#tCHtWPWE#tCStDStDHData55h30h10 for Chip EraseInProgressCompleteOE#tWPHtWHWH2tBUSYRY/BY#tVCSVCCtRBNote: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”..Figure 17.Chip/Sector Erase Operation Timings

40Am29LV065DJanuary 10, 2002

AC CHARACTERISTICS

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplementTrueValid DataHigh ZVAVAtCEtOEtDFDQ0–DQ6tBUSYRY/BY#Status DataStatus DataTrueValid DataHigh ZNote: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 18.Data# Polling Timings (DuringEmbeddedAlgorithms)

January 10, 2002Am29LV065D41

AC CHARACTERISTICS

tAHTAddressestAHTtASOCE#tOEHWE#tOEPHtCEPHtASOE#tDHDQ6/DQ2Valid DataValidStatustOEValidStatusValidStatusValid Data (first read)RY/BY#(second read)(stops toggling)Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle

Figure 19.Toggle Bit Timings (DuringEmbeddedAlgorithms)

EnterEmbeddedErasing

WE#

EraseSuspendEraseEnter EraseSuspend Program

EraseSuspendProgram

EraseResume

Erase Suspend

Read

Erase

EraseComplete

Erase SuspendRead

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

Figure 20.DQ2 vs. DQ6

42Am29LV065DJanuary 10, 2002

AC CHARACTERISTICSTemporary Sector Unprotect

ParameterJEDEC

StdtVIDRtRSPtRRB

Description

VID Rise and Fall Time (See Note)RESET# Setup Time for Temporary Sector Unprotect

RESET# Hold Time from RY/BY# High for Temporary Sector Group Unprotect

MinMinMin

All Speed Options

50044

Unitnsµsµs

Note: Not 100% tested.

VIDRESET#VSS, VIL,or VIHtVIDRProgram or Erase Command SequenceCE#tVIDRVIDVSS, VIL,or VIHWE#tRSPRY/BY#

tRRBFigure 21.Temporary Sector Group UnprotectTimingDiagram

January 10, 2002Am29LV065D43

AC CHARACTERISTICS

VIDVIHRESET#SA, A6,A1, A0Valid*Sector Group Protect or UnprotectValid*Verify40hSector Group Protect: 150 µs, Sector Group Unprotect: 15 msValid*Data60h60hStatus1 µsCE#WE#OE#* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22.Sector Group Protect and UnprotectTimingDiagram

44Am29LV065DJanuary 10, 2002

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

ParameterJEDECtAVAVtAVWLtELAXtDVEHtEHDXtGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH1tWHWH2

StdtWCtAStAHtDStDHtGHELtWStWHtCPtCPHtWHWH1tWHWH1tWHWH2

Description

Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time

Read Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse WidthCE# Pulse Width High

Byte Programming Operation (Note 2)

Accelerated Byte Programming Operation (Note 2)Sector Erase Operation (Note 2)

MinMinMinMinMinMinMinMinMinMinTypTypTyp

4590R90

Speed Options

101R100045000045301170.9

505050120R120

Unitnsnsnsnsnsnsnsnsnsnsµsµssec

Notes:

1.Not 100% tested.

2.See the “Erase And Programming Performance” section for more information.

January 10, 2002Am29LV065D45

AC CHARACTERISTICS

XXX for programXXX for erase PA for programSA for sector eraseXXX for chip erase Data# PollingPAAddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDStDHDatatRHA0 for program55 for erase PD for program30 for sector erase10 for chip erase tAStAHtWHWH1 or 2tBUSYDQ7#DOUTRESET#RY/BY#Notes:

1.Figure indicates last two bus cycles of a program or erase operation.

2.PA = program address, SA = sector address, PD = program data.

3.DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

Figure 23.Alternate CE# Controlled Write (Erase/Program)OperationTimings

46Am29LV065DJanuary 10, 2002

ERASE AND PROGRAMMING PERFORMANCE

ParameterSector Erase TimeChip Erase TimeByte Program Time

Accelerated Byte Program TimeChip Program Time (Note 3)

Typ (Note 1)

0.9112

150 120126Max (Note 2)

15

Unitsecsecµsµssec

Excludes system level overhead (Note 5)

Comments

Excludes 00h programming prior to erasure (Note 4)

Notes:

1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles.

3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4.In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

10 for further information on command definitions.

6.The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)

Input voltage with respect to VSS on all I/O pinsVCC Current

Min–1.0 V–1.0 V–100 mA

Max12.5 VVCC + 1.0 V+100 mA

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter Symbol

CINCOUTCIN2

Parameter DescriptionInput CapacitanceOutput CapacitanceControl Pin Capacitance

Test SetupVIN = 0VOUT = 0VIN = 0

Typ68.57.5

Max7.5129

UnitpFpFpF

Notes:

1.Sampled, not 100% tested.

2.Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Minimum Pattern Data Retention Time

Test Conditions

150°C125°C

Min1020

UnitYearsYears

January 10, 2002Am29LV065D47

PHYSICAL DIMENSIONSTS 048—48-Pin Standard Pinout Thin Small Outline Package(TSOP)Dwg rev AA; 10/9948Am29LV065DJanuary 10, 2002

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse Pinout Thin Small Outline Package(TSOP)

Dwg rev AA; 10/99January 10, 2002Am29LV065D49

PHYSICAL DIMENSIONS

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)11 x 12 mm package

Dwg rev AF; 10/9950Am29LV065DJanuary 10, 2002

REVISION SUMMARYRevision A (July 27, 2000)

Initial release.

Table 4, Sector Group Protection/Unprotection AddressTable

Corrected the sector group address bits for sectors–127.

Revision A+1 (August 4, 2000)

Global

Deleted references to the 48-pin reverse TSOP. Connection Diagrams

Corrected pin 36 on TSOP package to VIO.

Accelerated Program Operation, Unlock Bypass Command Sequence

Modified caution note regarding ACC input.

Revision B (January 10, 2002)

Global

Added TSR048 package. Clarified description of Ver-satileIO (VIO) in the following sections: DistinctiveCharacteristics; General Description; VersatileIO (VIO)Control; Operating Ranges; DC Characteristics;CMOS compatible.

Reduced typical sector erase time from 1.6 s to 0.9 s.Table 3, Am29LV065D Autoselect Codes, (HighVoltageMethod)

Corrected the autoselect code for sector protectionverification.

Sector Group Protection and UnprotectionDeleted reference to previous method of sector pro-tection and unprotection.

Autoselect Command SequenceClarified description of function.SecSi (Secured Silicon) Sector Flash MemoryRegion

Clarified the customer lockable version of this devicecan be programmed and protected only once. In Table5, changed address range in second row.DC Characteristics

Changed minimum VOH1 from 0.85VIO to 0.8VIO. De-leted reference to Note 6 for both VOH1 and VOH2.Erase and Program Operations table

Corrected to indicate tBUSY specification is a maximumvalue.

Erase and Program Performance table

Changed typical sector erase time from 1.6 s to 0.9 sand typical chip erase time from 205 s to 115 s.

Revision A+2 (August 14, 2000)

Ordering Information

Corrected 90 ns entry in VIO column for FBGA.

Revision A+3 (August 25, 2000)

Table 3, Am29LV065D Autoselect Codes, (HighVoltageMethod)

Corrected the SecSI Sector Indicator Bit codes from80h/00h to 90h/10h.

Revision A+4 (October 19, 2000)

Global

Changed data sheet status to “Preliminary.”

Revision A+5 (November 7, 2000)

Ordering InformationDeleted burn-in option.

Revision A+6 (November 27, 2000)

Pin Description, and Table 11, Write Operation Status

Deleted references to RY/BY# being available only onthe FBGA package. RY/BY# is also available on theTSOP package.

Revision A+7 (March 8, 2001)

Global

Deleted “Preliminary” status from document.

Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

January 10, 2002Am29LV065D51