MOTOROLASEMICONDUCTOR TECHNICAL DATAMC14558BBCD-to-Seven SegmentDecoderThe MC14558B decodes 4–bit binary coded decimal data dependent onthe state of auxiliary inputs, Enable and RBI, and provides an active–highseven–segment output for a display driver.An auxiliary input truth table is shown, in addition to the BCD toseven–segment truth table, to indicate the functions available with the twoauxiliary inputs.Leading Zero blanking is easily obtained with an external flip–flop in timedivision multiplexed systems displaying most significant decade first.••••••Supply Voltage Range = 3.0 Vdc to 18 VdcSegment Blanking for All Illegal Input CombinationsLamp Test FunctionCapability for Suppression of Non–Significant ZerosLamp Intensity FunctionCapable of Driving Two Low–power TTL Loads. One Low–powerSchottky TTL Load or Two HTL Loads Over the Rated TemperatureRangeL SUFFIXCERAMICCASE 620P SUFFIXPLASTICCASE 648D SUFFIXSOICCASE 751BORDERING INFORMATIONMC14XXXBCPMC14XXXBCLMC14XXXBDPlasticCeramicSOICTA = – 55° to 125°C for all packages.MAXIMUM RATINGS* (Voltages referenced to VSS)RatingDC Supply VoltageInput Voltage, All InputsDC Input Voltage, per PinOperating Temperature RangePower Dissipation, per Package†Storage Temperature RangeSymbolVDDVinIinTAPDTstgValue– 0.5 to + 18– 0.5 to VDD + 0.5± 10– 55 to + 125500– 65 to + 150UnitVVmAdc_CmW_CPIN ASSIGNMENTBCENABLERBORBIDAVSS12345678161514131211109VDDfgabcdeedfagbc*Maximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CCeramic “L” Packages: – 12 mW/_C From 100_C To 125_CDISPLAYAUXILIARY INPUT TRUTH TABLEEnablePin 300111RBIPin 50110XBCDInputCodeXX001 – 90RBOPin 401101Function PerformedLamp TestBlank SegmentsDisplay ZeroBlank Segments1–9 Displayed123456789X = Don’t Care RBI = Ripple Blanking Input RBO = Ripple Blanking OutputREV 31/94©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995MC14558B1ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicOutput VoltageVin = VDD or 0“0” LevelSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—5.010155.01015Min———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.2—————– 55_CMax0.050.050.05———1.53.04.0——————————±0.1—5.01020Min———4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40.511.33.4—————25_CTyp #0005.010152.254.506.752.755.508.25– 4.2– 0.88 – 2.25– 8.80.882.258.8±0.000015.00.0050.0100.015Max0.050.050.05———1.53.04.0——————————±0.17.55.01020125_CMin———4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.40.360.92.4—————Max0.050.050.05———1.53.04.0Vdc———mAdc———————±1.0—150300600mAdcUnitVdc“1” LevelVin = 0 or VDDInput Voltage“0” Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)“1” Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)Output Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)Input CurrentInput CapacitanceQuiescent Current(Per Package) Vin = 0 or VDDIout = 0 µATotal Supply Current**†(Dynamic plus Quiescent,Per Package) (CL = 50 pF on all outputs, all buffers switching)SourceVOHVdcVILVdcVIHIOHSinkIOLIinCinIDDµAdcpFµAdcITIT = (1.2 µA/kHz) f + IDDIT = (2.4 µA/kHz) f + IDDIT = (3.6 µA/kHz) f + IDDµAdc#Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level= 1.0 V min @ VDD = 5.0 V =2.0 V min @ VDD = 10 V =2.5 V min @ VDD = 15 V†To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDfwhere: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.**The formulas given are for the typical characteristics only at 25_C.This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however,it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to thishigh-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin orVout) ≤ VDD.Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).MC14558B2MOTOROLA CMOS LOGIC DATASWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C; see Figure 1)CharacteristicOutput Rise TimetTLH = (3.0 ns/pF) CL + 30 nstTLH = (1.5 ns/pF) CL + 15 nstTLH = (1.1 ns/pF) CL + 10 nsOutput Fall TimetTHL = (1.5 ns/pF) CL + 25 nstTHL = (0.75 ns/pF) CL + 12.5 nstTHL = (0.55 ns/pF) CL + 9.5 nsPropagation Delay TimetPLH = (1.7 ns/pF) CL + 495 nstPLH = (0.66 ns/pF) CL + 187 nstPLH = (0.5 ns/pF) CL + 120 nsPropagation Delay TimetPHL = (1.7 ns/pF) CL + 695 nstPHL = (0.66 ns/pF) CL + 242 nstPHL = (0.5 ns/pF) CL + 160 nsSymboltTLHVDD5.010155.010155.010155.01015Min———————————Typ10050401005040580220145780275185Max20010080UnitnstTHLns20010080ns1160440230ns1560550370tPLHtPHL*The formulae given are for the typical characteristics only.TRUTH TABLEInputsEnablePin 31111111111100RBIPin 51XXXXXXXXX001DPin 600000000110XXCPin 200001111000XXBPin 100110011000XXAPin 701010101010XXaPin 131011010111010bPin 121011100111010cPin 111001111111010dPin 101011011010010Outputs*ePin 91110001010010fPin 151100111011010gPin 140011111011010RBOPin 41111111111001BlankBlankDisplay*All non–valid BCD input codes produce a blank display.X = Don’t Care20 nsANY INPUT10%tPLH90%50%tPHL50%tTLH90%tTHL10%20 nsANY OUTPUTFigure 1. Signal WaveformsMOTOROLA CMOS LOGIC DATAMC14558B3LOGIC DIAGRAMabdegcRBO13121015f1411935712ENABLERBICMC14558B4DAB64MOTOROLA CMOS LOGIC DATATYPICAL APPLICATIONSN4N3N2N1N–1N–2N–3VSSRBIRBORBIRBORBIRBORBIRBORBIRBORBIRBORBIRBOEnLAMP TESTEnEnEnEnEnVSSEnFigure 2. Leading and Trailing ZeroSuppression with Lamp TestN4N3N2N1VDDN–1N–2N–3RBIRBORBIRBORBIRBORBIRBORBIRBORBIRBORBIRBOBLANKINGEnEnEnEnEnEnEnFigure 3. Leading and Trailing Zero Suppressionwith PWM Intensity Blanking and No Lamp TestN4N3N2N1N–1N–2N–3RBIRBORBIRBORBIRBORBIRBORBIRBORBIRBORBIRBOEnBLANKINGLAMP TESTEnEnEnEnEnEnFigure 4. Zero Suppression with Lamp Testand Intensity BlankingMOTOROLA CMOS LOGIC DATAMC14558B5OUTLINE DIMENSIONSL SUFFIXCERAMIC DIP PACKAGECASE 620–10ISSUE V–A–169NOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4.DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.DIMABCDEFGHKLMNINCHESMINMAX0.7500.7850.2400.295–––0.2000.0150.0200.050 BSC0.0550.0650.100 BSC0.0080.0150.1250.1700.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX19.0519.936.107.49–––5.080.390.501.27 BSC1.401.652.54 BSC0.210.383.184.317.62 BSC0 _15 _0.511.01–B–18CL–T–SEATINGPLANENEFDG16 PLKMJ16 PL0.25 (0.010)MMTBS0.25 (0.010)TASP SUFFIXPLASTIC DIP PACKAGECASE 648–08ISSUE R–A–169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMINMAX0.7400.7700.2500.2700.1450.1750.0150.0210.0400.700.100 BSC0.050 BSC0.0080.0150.1100.1300.2950.3050 _10 _0.0200.040MILLIMETERSMINMAX18.8019.556.356.853.694.440.390.531.021.772.54 BSC1.27 BSC0.210.382.803.307.507.740 _10 _0.511.01B18FSCL–T–HKGD16 PLSEATINGPLANEJTAMM0.25 (0.010)MMC14558B6MOTOROLA CMOS LOGIC DATAOUTLINE DIMENSIONSD SUFFIXPLASTIC SOIC PACKAGECASE 751B–05ISSUE J–A–NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSMINMAX9.8010.003.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3860.3930.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2290.2440.0100.019169–B–18P8 PL0.25 (0.010)MBSGFKC–T–SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TBSASDIMABCDFGJKMPRHow to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609INTERNET: http://Design–NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA CMOS LOGIC DATA
MC14558B
7