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CY7C1470BV33-167AXC资料

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined SRAM with NoBL™ Architecture

Features

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Functional Description

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burstSRAMs with No Bus Latency™ (NoBL™) logic, respectively.They are designed to support unlimited true back-to-back reador write operations with no wait states. The CY7C1470BV33,CY7C1472BV33, and CY7C1474BV33 are equipped with theadvanced (NoBL) logic required to enable consecutive read orwrite operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data insystems that require frequent read or write transitions. TheCY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pincompatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled bythe rising edge of the clock. All data outputs pass through outputregisters controlled by the rising edge of the clock. The clockinput is qualified by the Clock Enable (CEN) signal, which whendeasserted suspends operation and extends the previous clockcycle.

Write operations are controlled by the Byte Write Selectsfor(BWa–BWd for CY7C1470BV33, BWa–BWb

CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and aWrite Enable (WE) input. All writes are conducted with on-chipsynchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and anasynchronous Output Enable (OE) provide for easy bankselection and output tri-state control. To avoid bus contention,the output drivers are synchronously tri-stated during the dataportion of a write sequence.

Pin-compatible and functionally equivalent to ZBT™ Supports 250 MHz bus operations with zero wait states❐Available speed grades are 250, 200, and 167 MHzInternally self-timed output buffer control to eliminate the need to use asynchronous OE

Fully registered (inputs and outputs) for pipelined operationByte Write capabilitySingle 3.3V power supply3.3V/2.5V IO power supplyFast clock-to-output time

❐3.0 ns (for 250-MHz device)

Clock Enable (CEN) pin to suspend operationSynchronous self-timed writes

CY7C1470BV33, CY7C1472BV33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV33

available in Pb-free and non-Pb-free 209-ball FBGA packageIEEE 1149.1 JTAG Boundary Scan compatibleBurst capability—linear or interleaved burst order“ZZ” Sleep Mode option and Stop Clock option

■■■■■■

■■■

Selection Guide

Description

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

250 MHz3.0500120

200 MHz3.0500120

167 MHz3.4450120

UnitnsmAmA

CypressSemiconductorCorporationDocument #: 001-15031 Rev. *C

•198 Champion Court•

SanJose,CA95134-1709•408-943-2600

Revised February 29, 2008

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Logic Block Diagram – CY7C1470BV33 (2M x 36)

A0,A1,AADDRESSREGISTER0A1A1'A0D1Q1D0BURSTA0'MODELOGICQ0CLKCADV/LDCCENWRITEADDRESSWRITEADDRESSREGISTER1REGISTER2SOEUTDOUNPTUAPADV/LDSTTAUWRITEREGISTRYETRBWaANDDATACOHERENCYWRITEMEMORYEBWbCONTROLLOGICDRIVERSARRAYGSDQsBWAITBUcBWSEFDQPadMPTFDQPbEEEDQPcWESRRRDQPdSSENIGEINPUTINPUTREGISTER1EREGISTER0EOECE1READLOGICCE2CE3ZZSLEEPCONTROLLogic Block Diagram – CY7C1472BV33 (4M x 18)

A0,A1,AADDRESSREGISTER0A1A0D1Q1A1'MODED0BURSTLOGICQ0A0'CLKCADV/LDCCENWRITEADDRESSWRITEADDRESSREGISTER1REGISTER2OUOTUSPTADV/LDEUDPTAUWRITEREGISTRYNTTBWRAaANDDATACOHERENCYMEMORYSECONTROLLOGICWRITEEBDRIVERSARRAYAGSUDQsBWbMITFPSEFDQPaSTEEDQPbERRWERSSNIGEEINPUTREGISTER1EINPUTREGISTER0EOECE1READLOGICCE2CE3ZZControlSleepDocument #: 001-15031 Rev. *CPage 2 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Logic Block Diagram – CY7C1474BV33 (1M x 72)

A0,A1,AADDRESSREGISTER0A1A0D1Q1A1'MODED0BURSTA0'LOGICQ0CLKCADV/LDCCENWRITEADDRESSWRITEADDRESSREGISTER1REGISTER2OUOTUSPTADV/LDEUDPAUBWTTaWRITEREGISTRYNTABWbANDDATACOHERENCYMEMORYSRBBWSUDQscCONTROLLOGICWRITEDRIVERSARRAYEEAGBWITFdMPSEFDQPaBWeSTEEDQPbERRDQPcBWfRSBWgSNIDQPdGBWhEEDQPeDQPfDQPgDQPhWEINPUTREGISTER1EINPUTREGISTER0EOECE1READLOGICCE2CE3ZZControlSleepDocument #: 001-15031 Rev. *CPage 3 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Pin Configurations

Figure 1. 100-Pin TQFP Pinout

AACE1CE2BWdBWcBWbBWaCE3VDDVSSCLKWECENOEADV/LDAAAACE1CE2NCNCBWbBWaCE3VDDVSSCLKWECENOEADV/LDAANCNCNCVDDQVSSNCNCDQbDQbVSSVDDQ1234567101112131415161718192021222324252627282930AA1009997969594939291908887868584838281DQPcDQcDQcVDDQVSSDQcDQcDQc DQc VSSVDDQDQc DQcNC VDDNCVSSDQd DQd VDDQVSSDQdDQdDQdDQdVSSVDDQDQdDQdDQPd12345671011121314151617181920212223242526272829301009997969594939291908887868584838281DQPbDQbDQbVDDQVSSAA80797877767574737271706968676665636261605958575655535251ANCNCVDDQVSSNCDQPaDQa DQaVSSVDDQDQaDQaVSSNC VDDZZ DQaDQaVDDQVSSDQaDQaNCNCVSSVDDQNCNCNCCY7C1470BV33 (2M x 36)80797877767574737271706968676665636261605958575655535251DQbDQb DQb DQb VSSVDDQDQb DQbDQb DQbNCVSSVDDNC NCVDDVSSZZ DQbDQaDQaDQbVDDQVDDQVSSVSSDQaDQbDQaDQbDQaDQPbNCDQaVSSVSSVDDQVDDQNCDQaDQaNCDQPaNCCY7C1472BV33 (4M x 18)313233343536373839404142434447484950MODE AAAAA1A0MODE AAAAA1A0VSSVDDAAAAAAAAANC(288)NC(144)NC(288)NC(144)Document #: 001-15031 Rev. *C

VSSVDDAAAAAAAAA313233343536373839404142434447484950Page 4 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Pin Configurations (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1470BV33 (2M x 36)

1ABCDEFGHJKLMNPRNC/576MNC/1GDQPcDQcDQcDQcDQcNCDQdDQdDQdDQdDQPdNC/144MMODE2AANCDQcDQcDQcDQcNCDQdDQdDQdDQdNCAA3CE1CE2VDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA4BWcBWdVSSVDDVDDVDDVDDVDDVDDVDDVDDVDDVSSA5BWb BWaVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSNCTDITMS6CE3CLK7CENWE8ADV/LD9A10AANCDQbDQbDQbDQbNCDQaDQaDQaDQaNCAA11NCNCDQPbDQbDQbDQbDQbZZDQaDQaDQaDQaDQPaNC/288MAOEAVDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAAVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSNCA1A0VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSNCTDOTCKVSSVDDVDDVDDVDDVDDVDDVDDVDDVDDVSSAAACY7C1472BV33 (4M x 18)

ABCDEFGHJKLMNPR

NC/576MNC/1GNCNCNCNCNCNCDQbDQbDQbDQbDQPbNC/144MMODE

AANCDQbDQbDQbDQbNCNCNCNCNCNCAA

CE1CE2VDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

BWbNCVSSVDDVDDVDDVDDVDDVDDVDDVDDVDDVSSA

NCBWaVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSNCTDI

TMS

CE3CLK

CENWEVSS

ADV/LD

AANCNCNCNCNCNCDQaDQaDQaDQaNCAA

ANCDQPaDQaDQaDQaDQaZZNCNCNCNCNCNC/288MA

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSNCA1A0

OEVSS

AVDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQA

VSSVSSVSSVSSVSSVSSVSSVSSVSSNCTDOTCK

VDDVDDVDDVDDVDDVDDVDDVDDVDDVSSA

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Pin Configurations (continued)

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1474BV33 (1M × 72)

ABCDEFGHJKLMNPRTUVW

DQgDQgDQgDQgDQPgDQcDQcDQcDQcNCDQhDQhDQhDQhDQPdDQdDQdDQdDQd

DQgDQgDQgDQgDQPcDQcDQcDQcDQcNCDQhDQhDQhDQhDQPhDQdDQdDQdDQd

ABWScBWShVSSVDDQVSSVDDQVSSVDDQCLKVDDQVSSVDDQVSSVDDQVSSNC/144M

ATMS

CE2BWSgBWSdNCVDDQVSSVDDQVSSVDDQNCVDDQVSSVDDQVSSVDDQNCAATDI

ANCNC/576MNC/1GVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDNCAAA

ADV/LDWECE1OEVDDNCNCNCNCCENNCNCNCZZVDDMODEAA1A0

AANCNCVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDNCAAA

CE3BWSbBWSeNCVDDQVSSVDDQVSSVDDQNCVDDQVSSVDDQVSSVDDQNCAATDO

ABWSfBWSaVSSVDDQVSSVDDQVSSVDDQNCVDDQVSSVDDQVSSVDDQVSSNC/288M

ATCK

DQbDQbDQbDQbDQPfDQfDQfDQfDQfNCDQaDQaDQaDQaDQPaDQeDQeDQeDQe

DQbDQbDQbDQbDQPbDQfDQfDQfDQfNCDQaDQaDQaDQaDQPeDQeDQeDQeDQe

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 1. Pin DefinitionsPin NameA0A1ABWaBWbBWcBWdBWeBWfBWgBWhWEADV/LD

IO TypeInput-SynchronousInput-Synchronous

Pin Description

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK.

Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

Input-SynchronousInput-Synchronous

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input Used to Advance the On-chip Address Counter or Load a New

Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device.

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device.

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device.

Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automat-ically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQX. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.

CLKCE1CE2CE3OE

Input-ClockInput-SynchronousInput-SynchronousInput-SynchronousInput-Asynchronous

CEN

Input-SynchronousIO-Synchronous

DQS

DQPX

IO-Synchronous

MODE

Input Strap PinMode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE must not change states during operation. When left floating MODE defaults HIGH, to an interleaved burst order.JTAG Serial OutputSynchronous

Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.

TDO

TDI

JTAG Serial InputSerial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.Synchronous

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 1. Pin Definitions (continued)Pin NameTMSTCKVDDVDDQVSSNCNC(144M, 288M, 576M, 1G)ZZ

IO Type

Pin Description

Test Mode Select This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. SynchronousJTAG ClockPower SupplyGround––

Clock Input to the JTAG Circuitry.

Power Supply Inputs to the Core of the Device.

Ground for the Device. Should be connected to ground of the system.No Connects. This pin is not connected to the die.

These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G densities.

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull-down.

register and onto the data bus within 3.0 ns (250-MHz device)provided OE is active LOW. After the first clock of the readaccess the output buffers are controlled by OE and the internalcontrol logic. OE must be driven LOW to drive out the requesteddata. During the second clock, a subsequent operation (read,write, or deselect) can be initiated. Deselecting the device is alsopipelined. Therefore, when the SRAM is deselected at clock riseby one of the chip enable signals, its output tri-states followingthe next clock rise.

IO Power SupplyPower Supply for the IO Circuitry.

Input-Asynchronous

Functional Overview

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33are synchronous-pipelined Burst NoBL SRAMs designed specif-ically to eliminate wait states during read or write transitions. Allsynchronous inputs pass through input registers controlled bythe rising edge of the clock. The clock signal is qualified with theClock Enable input signal (CEN). If CEN is HIGH, the clock signalis not recognized and all internal states are maintained. Allsynchronous operations are qualified with CEN. All data outputspass through output registers controlled by the rising edge of theclock. Maximum access delay from the clock rise (tCO) is 3.0 ns(250-MHz device).

Accesses can be initiated by asserting all three Chip Enables(CE1, CE2, CE3) active at the rising edge of the clock. If CEN isactive LOW and ADV/LD is asserted LOW, the addresspresented to the device is latched. The access can either be aread or write operation, depending on the status of the WriteEnable (WE). BW[x] can be used to conduct Byte Write opera-tions.

Write operations are qualified by the Write Enable (WE). Allwrites are simplified with on-chip synchronous self-timed writecircuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and anasynchronous Output Enable (OE) simplify depth expansion. Alloperations (reads, writes, and deselects) are pipelined. ADV/LDmust be driven LOW after the device has been deselected toload a new address for the next operation.

Burst Read Accesses

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33have an on-chip burst counter that enables the user to supply asingle address and conduct up to four reads without reassertingthe address inputs. ADV/LD must be driven LOW to load a newaddress into the SRAM, as described in the Single ReadAccesses section. The sequence of the burst counter is deter-mined by the MODE input signal. A LOW input on MODE selectsa linear burst mode, a HIGH selects an interleaved burstsequence. Both burst counters use A0 and A1 in the burstsequence, and wraps around when incremented sufficiently. AHIGH input on ADV/LD increments the internal burst counterregardless of the state of chip enables inputs or WE. WE islatched at the beginning of a burst cycle. Therefore, the type ofaccess (read or write) is maintained throughout the burstsequence.

Single Write Accesses

Write accesses are initiated when the following conditions aresatisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,and CE3 are ALL asserted active, and (3) the signal WE isasserted LOW. The address presented to the address inputs isloaded into the Address Register. The write signals are latchedinto the Control Logic block.

On the subsequent clock rise the data lines are automaticallytri-stated regardless of the state of the OE input signal. Thisallows the external logic to present the data on DQ and DQP(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b forCY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h forCY7C1474BV33). In addition, the address for the subsequent

Single Read Accesses

A read access is initiated when the following conditions aresatisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,and CE3 are ALL asserted active, (3) the input signal WE isdeasserted HIGH, and (4) ADV/LD is asserted LOW. Theaddress presented to the address inputs is latched into theAddress Register and presented to the memory core and controllogic. The control logic determines that a read access is inprogress and allows the requested data to propagate to the inputof the output register. At the rising edge of the next clock therequested data is allowed to propagate through the output

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

access (read, write, or deselect) is latched into the AddressRegister (provided the appropriate control signals are asserted).On the next clock rise the data presented to DQ and DQP(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b forCY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h forCY7C1474BV33) (or a subset for byte write operations, see“Partial Write Cycle Description” on page11 for details) inputs islatched into the device and the write is complete.

The data written during the Write operation is controlled by BW(BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472BV33, andBWa,b,c,d,e,f,g,h for CY7C1474BV33) signals. TheCY7C1470BV33, CY7C1472BV33, and CY7C1474BV33provides Byte Write capability that is described in “Partial WriteCycle Description” on page11. Asserting the Write Enable input(WE) with the selected BW input selectively writes to only thedesired bytes. Bytes not selected during a Byte Write operationremain unaltered. A synchronous self-timed write mechanismhas been provided to simplify the write operations. Byte Writecapability has been included to greatly simplify read, modify, orwrite sequences, which can be reduced to simple Byte Writeoperations.

Because the CY7C1470BV33, CY7C1472BV33, andCY7C1474BV33 are common IO devices, data must not bedriven into the device while the outputs are active. The OE canbe deasserted HIGH before presenting data to the DQ and DQP(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b forCY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h forCY7C1474BV33) inputs. Doing so tri-states the output drivers.As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d forCY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, andDQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) areautomatically tri-stated during the data portion of a write cycle,regardless of the state of OE.

clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputsare ignored and the burst counter is incremented. The correctBW (BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472V33,and BWa,b,c,d,e,f,g,h for CY7C1474BV33) inputs must be drivenin each cycle of the burst write to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ placesthe SRAM in a power conservation “sleep” mode. Two clockcycles are required to enter into or exit from this “sleep” mode.While in this mode, data integrity is guaranteed. Accessespending when entering the “sleep” mode are not considered validnor is the completion of the operation guaranteed. The devicemust be deselected before entering the “sleep” mode. CE1, CE2,and CE3, must remain inactive for the duration of tZZREC after theZZ input returns LOW.

Table 2. Interleaved Burst Address Table (MODE = Floating or VDD)

FirstAddressA1,A000011011

SecondAddressA1,A001001110

ThirdAddressA1,A010110001

FourthAddressA1,A011100100

Table 3. Linear Burst Address Table (MODE = GND)

First AddressA1,A000011011

SecondAddressA1,A001101100

Third AddressA1,A010110001

FourthAddressA1,A011000110

Burst Write Accesses

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33has an on-chip burst counter that enables the user to supply asingle address and conduct up to four write operations withoutreasserting the address inputs. ADV/LD must be driven LOW toload the initial address, as described in “Single Write Accesses”on page8. When ADV/LD is driven HIGH on the subsequent

ZZ Mode Electrical Characteristics

ParameterIDDZZtZZStZZRECtZZItRZZI

Description

Sleep mode standby currentDevice operation to ZZZZ recovery timeZZ active to sleep currentZZ Inactive to exit sleep current

Test Conditions

ZZ > VDD − 0.2VZZ > VDD − 0.2VZZ < 0.2VThis parameter is sampledThis parameter is sampled

02tCYC

2tCYC

Min

Max1202tCYC

UnitmAnsnsnsns

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 4. Truth Table

The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.[1, 2, 3, 4, 5, 6, 7]

OperationDeselect CycleContinue

Deselect CycleRead Cycle(Begin Burst)Read Cycle

(Continue Burst)NOP/Dummy Read(Begin Burst)Dummy Read(Continue Burst)Write Cycle(Begin Burst)Write Cycle

(Continue Burst)NOP/Write Abort(Begin Burst)Write Abort

(Continue Burst)Ignore Clock Edge(Stall)Sleep Mode

Address UsedNoneNoneExternalNextExternalNextExternalNextNoneNextCurrentNone

CEHXLXLXLXLXXX

ZZLLLLLLLLLLLH

ADV/LD

LHLHLHLHLHXX

WEXXHXHXLXLXXX

BWxXXXXXXLLHHXX

OEXXLLHHXXXXXX

CENLLLLLLLLLLHX

CLKL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HX

DQTri-StateTri-StateData Out (Q)Data Out (Q)Tri-StateTri-StateData In (D)Data In (D)Tri-StateTri-State

-Tri-State

Notes

1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see “Partial Write Cycle Description” on page11 for details.2.Write is defined by WE and BW[a:d]. See “Partial Write Cycle Description” on page11 for details. 3.When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.4.The DQ and DQP pins are controlled by the current cycle and the OE signal. 5.CEN = H inserts wait states. 6.Device powers up deselected with the IOs in a tri-state condition, regardless of OE.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQP[a:d] = tri-state when OE is inactive or when the device is deselected, and DQs= data when OE is active.

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 5. Partial Write Cycle Description

The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.[1, 2, 3, 8]

Function (CY7C1470BV33)

Read

Write – No bytes writtenWrite Byte a – (DQa and DQPa)Write Byte b – (DQb and DQPb)Write Bytes b, a

Write Byte c – (DQc and DQPc)Write Bytes c, aWrite Bytes c, bWrite Bytes c, b, a

Write Byte d – (DQd and DQPd)Write Bytes d, aWrite Bytes d, bWrite Bytes d, b, aWrite Bytes d, cWrite Bytes d, c, aWrite Bytes d, c, bWrite All Bytes

WEHLLLLLLLLLLLLLLLL

BWdXHHHHHHHHLLLLLLLL

BWcXHHHHLLLLHHHHLLLL

BWbXHHLLHHLLHHLLHHLL

BWaXHLHLHLHLHLHLHLHL

Function (CY7C1472BV33)

Read

Write – No Bytes WrittenWrite Byte a – (DQa and DQPa)Write Byte b – (DQb and DQPb)Write Both Bytes

WEHLLLL

BWbxHHLL

BWaxHLHL

Function (CY7C1474BV33)

Read

Write – No Bytes WrittenWrite Byte X − (DQx and DQPx)Write All Bytes

WEHLLL

BWxxHLAll BW = L

Note

8.Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate Write is based on which Byte Write is active.

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IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33incorporates a serial boundary scan test access port (TAP). Thisport operates in accordance with IEEE Standard 1149.1-1990but does not have the set of functions required for full 1149.1compliance. These functions from the IEEE specification areexcluded because their inclusion places an added delay in thecritical speed path of the SRAM. Note that the TAP controllerfunctions in a manner that does not conflict with the operation ofother devices using 1149.1 fully compliant TAPs. The TAPoperates using JEDEC-standard 3.3V or 2.5V IO logic levels.The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33contains a TAP controller, instruction register, boundary scanregister, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAGfeature. To disable the TAP controller, TCK must be tied LOW(VSS) to prevent clocking of the device. TDI and TMS are inter-nally pulled up and may be unconnected. They may alternatelybe connected to VDD through a pull up resistor. TDO must be leftunconnected. During power up, the device comes up in a resetstate, which does not interfere with the operation of the device.Figure 2. TAP Controller State Diagram

1TEST-LOGICRESET00RUN-TEST/1SELECT1SELECT1IDLEDR-SCANIR-SCAN001CAPTURE-DR1CAPTURE-IR00SHIFT-DR0SHIFT-IR011EXIT1-DR1EXIT1-IR100PAUSE-DR0PAUSE-IR0110EXIT2-DR0EXIT2-IR11UPDATE-DRUPDATE-IR1010The 0/1 next to each state represents the value of TMS at therising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs arecaptured on the rising edge of TCK. All outputs are driven fromthe falling edge of TCK.

Document #: 001-15031 Rev. *CCY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controllerand is sampled on the rising edge of TCK. It is allowable to leavethis ball unconnected if the TAP is not used. The ball is pulled upinternally, resulting in a logic HIGH level.Test Data-In (TDI)

The TDI ball is used to serially input information into the registersand can be connected to the input of any of the registers. Theregister between TDI and TDO is chosen by the instruction thatis loaded into the TAP instruction register. For information aboutloading the instruction register, see the TAP Controller StateDiagram. TDI is internally pulled up and can be unconnected ifthe TAP is unused in an application. TDI is connected to the mostsignificant bit (MSB) of any register. (See TAP Controller BlockDiagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from theregisters. The output is active depending upon the current stateof the TAP state machine. The output changes on the falling edgeof TCK. TDO is connected to the least significant bit (LSB) of anyregister. (See TAP Controller State Diagram.)Figure 3. TAP Controller Block Diagram

0BypassRegister210SelectionTDICircuitryInstructionRegister SelectionCircuitryTDO313029...210IdentificationRegisterx.....210BoundaryScanRegisterTCKTMSTAPCONTROLLERPerforming a TAP Reset

A RESET is performed by forcing TMS HIGH (Vedges of TCK. This RESET does not affect the operation of theDD) for five risingSRAM and may be performed while the SRAM is operating.During power up, the TAP is reset internally to ensure that TDOcomes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls andscans data into and out of the SRAM test circuitry. Only oneregister can be selected at a time through the instruction register.Data is serially loaded into the TDI ball on the rising edge of TCK.Data is output on the TDO ball on the falling edge of TCK.

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Instruction Register

Three-bit instructions can be serially loaded into the instructionregister. This register is loaded when it is placed between the TDIand TDO balls as shown in the “TAP Controller Block Diagram”on page12. During power up, the instruction register is loadedwith the IDCODE instruction. It is also loaded with the IDCODEinstruction if the controller is placed in a reset state as describedin the previous section.

When the TAP controller is in the Capture-IR state, the two leastsignificant bits are loaded with a binary ‘01’ pattern to enable faultisolation of the board-level serial test data path.Bypass Register

To save time when serially shifting data through registers, it issometimes advantageous to skip certain chips. The bypassregister is a single-bit register that can be placed between theTDI and TDO balls. This shifts data through the SRAM withminimal delay. The bypass register is set LOW (VBYPASS instruction is executed.SS) when theBoundary Scan Register

The boundary scan register is connected to all the input andbidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of theRAM IO ring when the TAP controller is in the Capture-DR stateand is then placed between the TDI and TDO balls when thecontroller is moved to the Shift-DR state. The EXTEST,SAMPLE/PRELOAD and SAMPLE Z instructions can be used tocapture the contents of the IO ring.

The Boundary Scan Order tables show the order in which the bitsare connected. Each bit corresponds to one of the bumps on theSRAM package. The MSB of the register is connected to TDI andthe LSB is connected to TDO.Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit codeduring the Capture-DR state when the IDCODE command isloaded in the instruction register. The IDCODE is hardwired intothe SRAM and can be shifted out when the TAP controller is inthe Shift-DR state. The ID register has a vendor code and otherinformation described in “Identification Register Definitions” onpage17.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bitinstruction register. All combinations are listed in “IdentificationCodes” on page17. Three of these instructions are listed asRESERVED and must not be used. The other five instructionsare described in this section in detail.

The TAP controller used in this SRAM is not fully compliant to the1149.1 convention because some of the mandatory 1149.1instructions are not fully implemented.

The TAP controller cannot be used to load address data orcontrol signals into the SRAM and cannot preload the IO buffers.The SRAM does not implement the 1149.1 commands EXTESTor INTEST or the PRELOAD portion of SAMPLE/PRELOAD;rather, it performs a capture of the IO ring when these instruc-tions are executed.

Document #: 001-15031 Rev. *C

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Instructions are loaded into the TAP controller during the Shift-IRstate when the instruction register is placed between TDI andTDO. During this state, instructions are shifted through theinstruction register through the TDI and TDO balls. To executethe instruction after it is shifted in, the TAP controller is movedinto the Update-IR state.EXTEST

EXTEST is a mandatory 1149.1 instruction which is executedwhenever the instruction register is loaded with all 0s. EXTESTis not implemented in this SRAM TAP controller, and thereforethis device is not compliant to 1149.1. The TAP controller doesrecognize an all-0 instruction.

When an EXTEST instruction is loaded into the instructionregister, the SRAM responds as if a SAMPLE/PRELOADinstruction has been loaded. There is one difference between thetwo instructions. Unlike the SAMPLE/PRELOAD instruction,EXTEST places the SRAM outputs in a High-Z state.IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO balls and shifts the IDCODE out of thedevice when the TAP controller enters the Shift-DR state.The IDCODE instruction is loaded into the instruction registerduring power up or whenever the TAP controller is in a test logicreset state.SAMPLE Z

The SAMPLE Z instruction connects the boundary scan registerbetween the TDI and TDO balls when the TAP controller is in aShift-DR state. It also places all SRAM outputs into a High-Zstate.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. ThePRELOAD portion of this instruction is not implemented, so thedevice TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into theinstruction register and the TAP controller is in the Capture-DRstate, a snapshot of data on the inputs and bidirectional balls iscaptured in the boundary scan register.

The user must be aware that the TAP controller clock can onlyoperate at a frequency up to 20 MHz, while the SRAM clockoperates more than an order of magnitude faster. Because thereis a large difference in the clock frequencies, it is possible thatduring the Capture-DR state, an input or output may undergo atransition. The TAP may then try to capture a signal while intransition (metastable state). This does not harm the device, butthere is no guarantee as to the value that is captured.Repeatable results may not be possible.

To guarantee that the boundary scan register captures thecorrect value of a signal, the SRAM signal must be stabilizedlong enough to meet the TAP controller’s capture setup plus holdtime (tCS plus tCH).

The SRAM clock input might not be captured correctly if there isno way in a design to stop (or slow) the clock during aSAMPLE/PRELOAD instruction. If this is an issue, it is still

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possible to capture all other signals and simply ignore the valueof the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data byputting the TAP into the Shift-DR state. This places the boundaryscan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not imple-mented, putting the TAP to the Update-DR state while performinga SAMPLE/PRELOAD instruction has the same effect as thePause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction registerand the TAP is placed in a Shift-DR state, the bypass register isplaced between the TDI and TDO balls. The advantage of theBYPASS instruction is that it shortens the boundary scan pathwhen multiple devices are connected together on a board.Reserved

These instructions are not implemented but are reserved forTestClock(TCK)TestModeSelect(TMS)TestData-In(TDI)TestData-Out(TDO)Document #: 001-15031 Rev. *Cfuture use. Do not use these instructions.

Figure 4. TAP Timing

123456tTHtTLtCYCtTMSStTMSHtTDIStTDIHtTDOVtTDOXDON’TCAREUNDEFINEDPage 14 of 30

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TAP AC Switching Characteristics

Over the Operating Range[9, 10]ParameterClocktTCYCtTFtTHtTLtTDOVtTDOXtTMSStTDIStCS

Hold TimestTMSHtTDIHtCH

TMS Hold after TCK Clock RiseTDI Hold after Clock RiseCapture Hold after Clock Rise

555

nsnsns

TCK Clock Cycle TimeTCK Clock FrequencyTCK Clock HIGH timeTCK Clock LOW timeTCK Clock LOW to TDO ValidTCK Clock LOW to TDO InvalidTMS Setup to TCK Clock RiseTDI Setup to TCK Clock RiseCapture Setup to TCK Rise

05552020

nsMHznsnsnsnsnsnsns

Description

Min

Max

Unit

Output Times

Setup Times

Notes

9.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

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3.3V TAP AC Test Conditions

Input pulse levels.................................................VSS to 3.3VInput rise and fall times....................................................1 nsInput timing reference levels...........................................1.5VOutput reference levels..................................................1.5VTest load termination supply voltage..............................1.5V

2.5V TAP AC Test Conditions

Input pulse levels.................................................VSS to 2.5VInput rise and fall time.....................................................1 nsInput timing reference levels........................................1.25VOutput reference levels................................................1.25VTest load termination supply voltage............................1.25V

3.3V TAP AC Output Load Equivalent

1.5V50ΩTDOZ =50ΩO20pF2.5V TAP AC Output Load Equivalent

1.25V50ΩTDOZ =O50Ω20pFTAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]

ParameterVOH1VOH2VOL1VOL2VIHVILIX

Description

Test Conditions

Min2.42.02.92.1

0.40.40.20.2

2.01.7–0.3–0.3–5

VDD + 0.3VDD + 0.30.80.75Max

UnitVVVVVVVVVVVVµA

Output HIGH VoltageIOH = –4.0 mA,VDDQ = 3.3V

IOH = –1.0 mA,VDDQ = 2.5VOutput HIGH VoltageIOH = –100 µAOutput LOW VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput Load Current

GND < VIN < VDDQIOL = 8.0 mAIOL = 1.0 mAIOL = 100 µA

VDDQ = 3.3VVDDQ = 2.5VVDDQ = 3.3VVDDQ = 2.5VVDDQ = 3.3VVDDQ = 2.5VVDDQ = 3.3VVDDQ = 2.5VVDDQ = 3.3VVDDQ = 2.5V

Note

11.All voltages refer to VSS (GND).

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Table 6. Identification Register Definitions

Instruction FieldRevision Number (31:29)Device Depth (28:24)[12]Architecture/Memory Type(23:18)

Bus Width/Density(17:12)Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

CY7C1470BV33

(2M x 36)

0000101100100010010000000110100

CY7C1472BV33

(4M x 18)

0000101100100001010000000110100

CY7C1474BV33

(1M x 72)

0000101100100011010000000110100

Description

Describes the version numberReserved for internal useDefines memory type and archi-tecture

Defines width and densityEnables unique identification of SRAM vendor

Indicates the presence of an ID register

Table 7. Scan Register Sizes

InstructionBypassID

Boundary Scan Order – 165 FBGABoundary Scan Order – 209 FBGATable 8. Identification Codes

InstructionEXTESTIDCODESAMPLE ZRESERVEDSAMPLE/PRELOAD

Code000001010011100

Description

Captures IO ring contents. Places the boundary scan register between TDI and TDO.Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations.

Captures IO ring contents. Places the boundary scan register between TDI and TDO.Forces all SRAM output drivers to a High-Z state.Do Not Use: This instruction is reserved for future use.

Captures IO ring contents. Places the boundary scan register between TDI and TDO.Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant.Do Not Use: This instruction is reserved for future use.Bit Size (x36)

313271-Bit Size (x18)

313252-Bit Size (x72)

3132-110

RESERVED101

Note

12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

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Table 9. Boundary Scan Exit Order (2M x 36)Bit #165-Ball ID

Bit #165-Ball ID

1C121R32D122P23E123R44D224P65E225R66F126R87G127P38F228P49G229P810J130P911K131P1012L132R913J233R1014M134R1115N135N1116K236M1117L237L1118M238M1019R139L1020

K11

Table 10. Boundary Scan Exit Order (4M x 18)Bit #165-Ball ID

Bit #165-Ball ID

1D214R42E215P63F216RG217R85J118P36K119P47L120P88M121P99N122P1010R123R911R224R1012R325R1113

M10

Document #: 001-15031 Rev. *CBit #165-Ball ID

41J1142K1043J1044H1145G1146F1147E1148D1049D1150C1151G1052F1053E10A955B956A1057B1058A859B860

Bit #165-Ball ID

27L1028K1029J1030H1131G1132F1133E1134D1135C1136A1137A938B939

A10

Bit #165-Ball ID

61B762B663A6B565A566A467B468B369A370A271

Bit #165-Ball ID

40B1041A842B843A744B745B6A7B8A449B350A351A252

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Boundary Scan Exit Order (1M x 72)

Bit #209-Ball ID

1A129T12A230T23B131U14B232U25C133V16C234V27D135W18D236W29E137T610E238V311F139V412F240U413G141W514G242V615H143W616H244V517J145U518J246U619L147W720L248V721M149U722M250V823N151V924N252W1125P153W1026P2V1127R255V1028

U11

Document #: 001-15031 Rev. *CBit #209-Ball ID

57U1058T1159T1060R1161R1062P1163P10N1165N1066M1167M1068L1169L1070P671J1172J1073H1174H1075G1176G1077F1178F1079E1080E1181D1182D1083C1184

C10

Bit #209-Ball ID

85B1186B1087A1188A10A790A591A992U3A694D695K696B697K398A9B4100B3101C3102C4103C8104C9105B9106B8107A4108C6109B7110

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Maximum Ratings

Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°CAmbient Temperature with

Power Applied............................................–55°C to +125°CSupply Voltage on VDD Relative to GND........–0.5V to +4.6VSupply Voltage on VDDQ Relative to GND.......–0.5V to +VDDDC to Outputs in Tri-State....................–0.5V to VDDQ + 0.5V

DC Input Voltage...................................–0.5V to VDD + 0.5VCurrent into Outputs (LOW)........................................20 mAStatic Discharge Voltage.......................................... > 2001V(MIL-STD-883, Method 3015)

Latch Up Current................................................... > 200 mA

Operating Range

RangeCommercialIndustrial

AmbientTemperature0°C to +70°C –40°C to +85°C

VDD3.3V –5%/+10%

VDDQ2.5V – 5%to VDD

Electrical Characteristics

Over the Operating Range[13, 14]ParameterVDDVDDQVOHVOLVIHVILIX

DescriptionPower Supply VoltageIO Supply VoltageOutput HIGH VoltageOutput LOW VoltageInput HIGH Voltage[13]Input LOW Voltage[13]For 3.3V IOFor 2.5V IO

For 3.3V IO, IOH = −4.0 mAFor 2.5V IO, IOH= −1.0 mAFor 3.3V IO, IOL= 8.0 mAFor 2.5V IO, IOL= 1.0 mAFor 3.3V IOFor 2.5V IOFor 3.3V IOFor 2.5V IO

Input Leakage Current GND ≤ VI ≤ VDDQexcept ZZ and MODE

Input Current of MODEInput = VSS

Input = VDD

Input Current of ZZ

IOZIDD [15]Input = VSSInput = VDD

Output Leakage CurrentGND ≤ VI ≤ VDDQ, Output DisabledVDD Operating Supply VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4.0-ns cycle, 250 MHz5.0-ns cycle, 200 MHz6.0-ns cycle, 167 MHz

ISB1

Automatic CE Power Down

Current—TTL Inputs

Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHzVIN ≥ VIH or VIN ≤ VIL,

5.0-ns cycle, 200 MHz

f = fMAX = 1/tCYC

6.0-ns cycle, 167 MHz

–5–5

305500500450245245245120

2.01.7–0.3–0.3–5–30

Test Conditions

Min3.1353.1352.3752.42.0

0.40.4VDD + 0.3VVDD + 0.3V

0.80.75Max3.6VDD2.625

UnitVVVVVVVVVVVμAμAμAμAμAμAmAmAmAmAmAmAmA

ISB2

Automatic CEMax. VDD, Device Deselected, All speed gradesPower Down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputsf = 0

Notes

13.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC)> –2V (pulse width less than tCYC/2).14.TPower-up: assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.15.The operation current is calculated with 50% read cycle and 50% write cycle.

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Electrical Characteristics

Over the Operating Range[13, 14] (continued)ParameterISB3

Description

Test Conditions

Min

Max245245245135

UnitmAmAmAmA

Automatic CE Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHzPower Down VIN ≤ 0.3V or VIN > VDDQ − 0.3V,

5.0-ns cycle, 200 MHz

Current—CMOS Inputsf = fMAX = 1/tCYC

6.0-ns cycle, 167 MHzAutomatic CEPower Down

Current—TTL Inputs

Max. VDD, Device Deselected, All speed gradesVIN ≥ VIH or VIN ≤ VIL, f = 0

ISB4

Capacitance

Tested initially and after any design or process changes that may affect these parameters.ParameterCADDRESSCDATACCTRL CCLKCIO

Description

Address Input CapacitanceData Input CapacitanceControl Input CapacitanceClock Input CapacitanceInput/Output Capacitance

Test ConditionsTA = 25°C, f = 1 MHz,

VDD = 3.3VVDDQ = 2.5V

100 TQFPMax

65865

165 FBGA209 FBGAMaxMax

65865

UnitpFpFpFpFpF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.Parameters

ΘJAΘJC

DescriptionThermal Resistance

(Junction to Ambient)Thermal Resistance (Junction to Case)

Test Conditions

Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51.

100 TQFP Package24.632.28

165 FBGA 209 FBGA UnitPackagePackage16.32.1

15.21.7

°C/W°C/W

AC Test Loads and Waveforms

3.3V IO Test Load

OUTPUT

Z0= 50Ω

3.3V

OUTPUT

RL= 50Ω

5pF

R = 351ΩR = 317Ω

VDDQGND

10%

ALL INPUT PULSES

90%

90%10%

≤1 ns

VL= 1.5V≤1 ns

(a)

2.5V IO Test Load

OUTPUT

Z0= 50Ω

2.5V

INCLUDINGJIG ANDSCOPE

(b)

R = 1667Ω

VDDQ

(c)

ALL INPUT PULSES10%

90%

90%10%

≤1 ns

OUTPUT

RL= 50Ω

5pF

VL= 1.25V

R = 1538Ω

GND

≤1 ns

(a)

INCLUDINGJIG ANDSCOPE

(b)

(c)

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Switching Characteristics

Over the Operating Range. Timing reference is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. Test conditions shown in(a) of “AC Test Loads and Waveforms” on page21 unless otherwise noted.

ParametertPower[16]ClocktCYCFMAXtCHtCL

Output TimestCOtOEVtDOHtCHZtCLZtEOHZtEOLZ

Setup TimestAStDStCENStWEStALStCES

Hold TimestAHtDHtCENHtWEHtALHtCEH

Address Hold After CLK RiseData Input Hold After CLK RiseCEN Hold After CLK RiseWE, BWx Hold After CLK RiseADV/LD Hold after CLK RiseChip Select Hold After CLK Rise

0.40.40.40.40.40.4

0.50.50.50.50.50.5

nsnsnsnsnsns

Address Setup Before CLK RiseData Input Setup Before CLK RiseCEN Setup Before CLK RiseWE, BWx Setup Before CLK RiseADV/LD Setup Before CLK RiseChip Select Setup

1.41.41.41.41.41.4

1.51.51.51.51.51.5

nsnsnsnsnsns

Data Output Valid After CLK RiseOE LOW to Output ValidData Output Hold After CLK RiseClock to High-Z[17, 18, 19]Clock to Low-Z[17, 18, 19]OE HIGH to Output High-Z[17, 18, 19]OE LOW to Output Low-Z[17, 18, 19]01.3

3.0

1.3

3.0

1.3

3.0

3.03.0

1.3

3.0

1.5

3.4

3.03.0

1.5

3.43.43.4

nsnsnsnsnsnsns

Clock Cycle Time

Maximum Operating FrequencyClock HIGHClock LOW

2.02.04.0

250

2.02.05.0

200

2.22.26.0

167

nsMHznsns

Description

VCC (typical) to the First Access Read or Write

–250 Min1

Max

1–200 Min

Max

Min1–167

Max

Unitms

Notes

16.This part has an internal voltage regulator; tpower is the time power is supplied above VDD minimum initially, before a read or write operation can be initiated.17.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of “AC Test Loads and Waveforms” on page21. Transition is measured ±200 mV

from steady-state voltage.

18.At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions.19.This parameter is sampled and not 100% tested.

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CY7C1472BV33, CY7C1474BV33

Switching Waveforms

Figure5 shows read-write timing waveform.[20, 21, 22]

Figure 5. Read/Write Timing

1CLKtCENStCENH2tCYC3456710tCHtCLCENtCEStCEHCEADV/LDWEBWxADDRESStASA1tAHA2tDStDHA3A4tCOtCLZtDOHA5tOEVA6tCHZA7DataIn-Out(DQ)OEWRITED(A1)WRITED(A2)D(A1)D(A2)D(A2+1)Q(A3)Q(A4)tOEHZQ(A4+1)D(A5)Q(A6)tDOHtOELZBURSTWRITED(A2+1)READQ(A3)READQ(A4)BURSTREADQ(A4+1)WRITED(A5)READQ(A6)WRITED(A7)DESELECTDON’TCAREUNDEFINEDNotes

20.For this waveform ZZ is tied LOW.

21.When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.22.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.

Document #: 001-15031 Rev. *CPage 23 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Switching Waveforms (continued)

Figure6 shows NOP, STALL and DESELECT Cycles waveform.

[20, 21, 23]

Figure 6. NOP, STALL and DESELECT Cycles

1CLKCENCEADV/LDWEBWxADDRESSA123456710A2A3A4A5tCHZDataIn-Out(DQ)WRITED(A1)READQ(A2)STALLD(A1)Q(A2)Q(A3)D(A4)Q(A5)READQ(A3)WRITED(A4)STALLNOPREADQ(A5)DESELECTCONTINUEDESELECTDON’TCARE[24, 25]UNDEFINEDFigure7 shows ZZ Mode timing waveform.Figure 7. ZZ Mode Timing

CLKtZZtZZRECZZtZZIISUPPLYIDDZZtRZZIDESELECTorREADOnlyALLINPUTS(exceptZZ)Outputs(Q)High-ZDON’TCARENotes

23.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.24.Device must be deselected when entering ZZ mode. See “Truth Table” on page10 for all possible signal conditions to deselect the device.25.IOs are in High-Z when exiting ZZ sleep mode.

Document #: 001-15031 Rev. *CPage 24 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visitwww.cypress.com for actual products offered.Speed(MHz)167

Ordering CodeCY7C1470BV33-167AXCCY7C1472BV33-167AXCCY7C1470BV33-167BZCCY7C1472BV33-167BZC

CY7C1470BV33-167BZXC51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-freeCY7C1472BV33-167BZXCCY7C1474BV33-167BGCCY7C1474BV33-167BGXCCY7C1470BV33-167AXICY7C1472BV33-167AXICY7C1470BV33-167BZICY7C1472BV33-167BZICY7C1470BV33-167BZXICY7C1472BV33-167BZXICY7C1474BV33-167BGICY7C1474BV33-167BGXI200

CY7C1470BV33-200AXCCY7C1472BV33-200AXCCY7C1470BV33-200BZCCY7C1472BV33-200BZC

CY7C1470BV33-200BZXC51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-freeCY7C1472BV33-200BZXCCY7C1474BV33-200BGCCY7C1474BV33-200BGXCCY7C1470BV33-200AXICY7C1472BV33-200AXICY7C1470BV33-200BZICY7C1472BV33-200BZICY7C1470BV33-200BZXICY7C1472BV33-200BZXICY7C1474BV33-200BGICY7C1474BV33-200BGXI

51-85167209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)51-85167209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

51-85050100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free

lndustrial

51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)51-85167209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

51-85050100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free

Commercial

51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)51-85167209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

51-85050100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free

lndustrial

51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)PackageDiagram

Part and Package Type

OperatingRangeCommercial

51-85050100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free

Document #: 001-15031 Rev. *CPage 25 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visitwww.cypress.com for actual products offered.Speed(MHz)250

Ordering CodeCY7C1470BV33-250AXCCY7C1472BV33-250AXCCY7C1470BV33-250BZCCY7C1472BV33-250BZC

CY7C1470BV33-250BZXC51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-freeCY7C1472BV33-250BZXCCY7C1474BV33-250BGCCY7C1474BV33-250BGXCCY7C1470BV33-250AXICY7C1472BV33-250AXICY7C1470BV33-250BZICY7C1472BV33-250BZICY7C1470BV33-250BZXICY7C1472BV33-250BZXICY7C1474BV33-250BGICY7C1474BV33-250BGXI

51-85167209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)51-85167209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free

51-85050100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free

Industrial

51-85165165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)PackageDiagram

Part and Package Type

OperatingRangeCommercial

51-85050100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free

Document #: 001-15031 Rev. *CPage 26 of 30

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Package Diagrams

Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050

16.00±0.2014.00±0.10100811800.30±0.080021..00±±0000..20220.65TYP.30513150R0.08MIN.0.20MAX.0°MIN.STAND-OFF0.250.05MIN.0.15MAX.GAUGEPLANE0°-7°R0.08MIN.0.20MAX.0.60±0.150.20MIN.1.00REF.DETAILADocument #: 001-15031 Rev. *C1.40±0.0512°±1°(8X)SEEDETAILA0.20MAX.1.60MAX.01.0SEATINGPLANENOTE:1.JEDECSTDREFMS-0262.BODYLENGTHDIMENSIONDOESNOTINCLUDEMOLDPROTRUSION/ENDFLASHMOLDPROTRUSION/ENDFLASHSHALLNOTEXCEED0.0098in(0.25mm)PERSIDEBODYLENGTHDIMENSIONSAREMAXPLASTICBODYSIZEINCLUDINGMOLDMISMATCH3.DIMENSIONSINMILLIMETERS51-85050-*BPage 27 of 30

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Package Diagrams (continued)

Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165

TOPVIEWPIN1CORNER12345671011ABCDEFGHJKLMNPR50.C5000±.150.23+0-.5C0.05513..00SEATINGPLANEC6.3X.0AM04.1Document #: 001-15031 Rev. *CBOTTOMVIEWPIN1CORNERØ0.05MCØ0.25MCABØ0.45±0.05(165X)11109876321AB0C0.1DEFG010.00.±4H100.J71K0L0.7MNPRA5.001.0010.00B15.00±0.100.15(4X)51-85165-*APage 28 of 30

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Package Diagrams (continued)

Figure 10. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167

Document #: 001-15031 Rev. *C51-85167-**Page 29 of 30

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Document History Page

Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 001-15031REV.***A*B*C

ECN No.103221744720824872159486

Issue DateSee ECNSee ECNSee ECNSee ECN

Orig. of Change

VKN/KKVTMPNew Data SheetVKN/AESAVKNVKN/PYRS

Added footnote 15 related to IDDConverted from preliminary to finalMinor Change-Moved to the external web

Description of Change

© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be usedfor medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for useas critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-supportsystems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-15031 Rev. *CRevised February 29, 2008Page 30 of 30

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in thisdocument may be the trademarks of their respective holders.

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