专利名称：Buffer with inductance-based capacitive-load
reduction
发明人：Jinghong Chen申请号：US11526306申请日：20060925
公开号：US20080074149A1公开日：20080327
专利附图：
摘要：A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In oneembodiment, the buffer circuit has one or more stages, each stage having one CMOSinverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is
coupled to a stage input and a stage output. Additionally, at least one stage of thebuffer circuit has two inductors, each coupled between a different voltage reference forthe buffer circuit and the stage output. One inductor has a PMOS transistor coupled tothe gate of an NMOS transistor and the other inductor has an NMOS transistor coupledto the gate of a PMOS transistor. When driving capacitive loads, the inductors partiallytune out the apparent load capacitance CL, thereby improving the charging capabilities ofinverter and enabling quicker charge and discharge times. Furthermore, partially tuningout apparent load capacitance facilitates the driving of larger capacitive loads.
申请人：Jinghong Chen
地址：Basking Ridge NJ US
国籍：US
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