VHDL简易交通灯设计

VHDL简易红绿灯设计报告

设计源文件： ---------------------------------------------------------------------------------- -- Company: -- Engineer: --

-- Create Date: 15:10:09 06/09/2009 -- Design Name:

-- Module Name: myslef - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_11.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity myslef is

Port ( RST : in STD_LOGIC; CLKIN : in STD_LOGIC;

LIGHT : out STD_LOGIC_VECTOR (2 downto 0)); end myslef;

architecture Behavioral of myslef is signal CLK_DIV:STD_LOGIC:='0';

signal CLK_DIV_REG:STD_LOGIC:='0';

signal LIGHTN:STD_LOGIC_VECTOR (2 downto 0):=\"001\"; CONSTANT N:Integer:=25000000;

CONSTANT P:Integer:=12;

signal counter:Integer range 0 to N; signal counter1:Integer range 0 to P;

begin

process(RST,CLKIN,LIGHTN) begin

LIGHT <= LIGHTN;

IF rising_edge(CLKIN)THEN IF(RST='1') then CLK_DIV <='0'; IF Counter=N then counter<=0;

CLK_DIV<=not CLK_DIV; else

counter<=counter+1; end if; end if; end if; end process;

process(CLKIN) begin if(CLKIN'EVENT AND CLKIN='1') then CLK_DIV_REG <= CLK_DIV; end if; end process;

process(RST,CLKIN) begin

if(RST='0' AND rising_edge(CLKIN)) then

if((CLK_DIV='1') and (CLK_DIV_REG='0')) then counter1<=counter1+1; if(counter1<=1)then LIGHTN<=\"010\"; elsif(counter1<=6)then LIGHTN<=\"100\"; elsif(counter1<=12)then LIGHTN<=\"001\"; else counter1<=0; end if; end if; end if;

end process; end Behavioral; Testbench测试文件： LIBRARY ieee;

USE ieee.std_logic_11.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;

ENTITY myslef_tb IS END myslef_tb;

ARCHITECTURE behavior OF myslef_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT myslef PORT(

RST : IN std_logic; CLKIN : IN std_logic;

LIGHT : OUT std_logic_vector(2 downto 0) );

END COMPONENT;

--Inputs

signal RST : std_logic := '0'; signal CLKIN : std_logic := '0';

--Outputs

signal LIGHT : std_logic_vector(2 downto 0); constant CLKIN_period :time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: myslef PORT MAP ( RST => RST,

CLKIN => CLKIN, LIGHT => LIGHT );

-- No clocks detected in port list. Replace below with -- appropriate port name

CLKIN_process :process begin CLKIN <= '0'; wait for CLKIN_period/2; CLKIN <= '1'; wait for CLKIN_period/2; end process;

-- Stimulus process stim_proc: process begin

-- hold reset state for 100ms. RST<='1'after 200 ns;

wait for 100ms;

wait for CLKIN_period*10;

-- insert stimulus here

wait; end process;

END; 仿真图：

系统功能框图： 电路结构： 工作流程：CLKIN脉冲时钟经过分频后激活触发器，触发器激活计数器计数，计数器为12进制计数器，当有不同计数值时，红绿黄灯分别亮起。